Real-time data acquisition system based on ADmC812 and DSP

　　Introduction

　　ADmC812 is ADI's new micro-converter with 8051 (8052) core as the control core. Because ADmC812 integrates a large number of peripheral devices. It itself is a fully programmable, self-calibrating, high-precision data acquisition system that can replace the traditional MCU+A/D+ROM+RAM high-cost, large-volume products, especially its high-precision and high-speed A/D Module, especially suitable for intelligent sensing, instant acquisition, data collection and various communication systems. However, for occasions where a large amount of data needs to be collected, complex operations, and high real-time requirements are required, it is often unable to meet the requirements due to limitations in structure and speed. In response to this situation, this article proposes a data acquisition system based on ADmC812 and DSP. In this system, ADmC812 serves as the host, completing functions such as ADC, DAC, display, keyboard, etc., while the DSP serves as the slave, focusing on complex data operations. The two implement data exchange and communication through general-purpose SRAM.

　　Introduction to ADmC812 and TMS320F206

　　ADmC812 microconversion chip

　　ADmC812 is an 8051/8052 microcontroller with 16-bit counting/timing and 32 programmable I/O interfaces. It has a built-in 8-channel, 5ms conversion time, precision self-correction, 12-bit successive approximation ADC; two 12-bit DACs , 10.5KB flash EEPROM, 256 bytes SRAM. It also includes some important functional modules, such as watchdog timer and power monitor, DMA mode between ADC and data memory, storage protection function, a universal asynchronous serial transceiver (UART), SPI and I2C bus interface.

　　The rich peripherals in ADmC812 enable it to form a complete data acquisition system without external bus expansion, which is very cost-effective. What is more noteworthy is that ADmC812 integrates 8 channels of 12-bit high-precision, self-calibrated 4ppm/℃ ADC circuits. Moreover, when the working conditions (such as clock frequency, analog input range, reference voltage or power supply voltage) change, in order to obtain high-precision ADC results, software can be used to set the four special function registers in the ADmC812 for correction. To achieve the purpose of further calibrating the ADC. ADmC812 can make the ADC work in 3 different modes by setting the three special function registers ADCON1~3 to achieve single conversion, continuous conversion and A/D conversion in DMA mode. You can choose according to specific needs. In DMA mode , allowing the ADC to continuously sample after each setting of the register ADCCON1~3, and write the results to the external RAM. This automatic capture function greatly facilitates data exchange between master and slave processors.

　　Digital signal processor TMS320F206

　　TMS320F206 (hereinafter referred to as F206) is one of the TMS320C2000 series DSPs produced by TI. It is a low-price, high-performance 16-bit fixed-point DSP launched after C2X and C5X. Since it adopts an improved Harvard structure, it has separate program bus and data bus, and adopts four-level pipeline operation, its operating speed can reach 40MIPS. High-speed operation characteristics. At the same time, it provides a rich instruction set and enhanced modular structure design, which improves its versatility and expands its application fields. It has now become an ideal substitute for high-end microcontrollers. The F206 has 32K of flash memory on-chip. Through the F206's own JTAG interface that complies with IEEE standard 1149.1, users can simulate and debug the program and burn the program code into the chip, which greatly facilitates the user's system. Design and program debugging.

　　TMS320F206 provides direct memory access (DMA) functionality, allowing direct memory access to external programs, data, and I/O space through the use of HOLD operations. This process is controlled by two signals. An external device can drive the pin low, thereby requesting control of the external bus. If the interrupt line is enabled, an interrupt will be triggered. When F206 interrupts the corresponding interrupt, the software logic can cause the processor to send a response signal, indicating that it will give up control of the external bus. According to the external address signal (A15~A0), data signal (D15~D0) and memory control signal (,,,,,,,) are set to a high-impedance state to implement the DMA function.

　　System hardware design

　　The hardware structure of the system is shown in Figure 1. The memory 62256 serves as the global data memory of the DSP and is also the external memory of the ADmC812. The two controllers are connected to the data memory 62256 through the bus to realize memory sharing. In order to ensure that the two controllers can work independently. Four pieces of 74HC245 are inserted between ADmC812 and 62256 for bus isolation. In this way, under the control of ADmC812, only one controller accesses 62256 at a time. In the figure, 62256 is used as the external memory of ADmC812, A15 is the chip select signal, and the address range is 8000H~FFFFH; as the global data memory of F206, it is used as the chip select line, using the high-end 32K word address range (8000H~FFFFH). The two chip select signals are connected to the chip select line CS2 of the 62256 through a NAND gate to achieve isolation of the chip select signals.

　　ADmC812 is connected to the DSP and XF pins through P1.0 and P3.2 (INT0) respectively. P1.0 applies for bus control from the DSP. After the DSP responds to the ADmC812 request, the DSP CPU is suspended and transfers the external bus. . ADmC812 turns on the bus driver through A15, and selects 62256 through the NAND gate to obtain control of 62256 and realize read and write operations on 62256. F206 can also request an interrupt from ADmC812, and ADmC812 will process related transactions after responding to the interrupt INT0. On the other hand, ADmC812 can confirm whether F206 is suspended by reading the level of the pin; and by controlling the pin, the branch transfer of the F206 program can be realized, increasing the flexibility of the system.

　　The entire system is divided into transaction module and data processing module. ADmC812 controls the transaction module and performs functions such as data collection, LED display, switch input and output, analog output and serial communication. F206 controls the data processing module, which mainly processes data and completes complex algorithms. In addition, some important export control functions can also be directly processed based on the data processing results to make up for the shortcomings of the ADmC812 I/O ports and speed up the system's response speed. Two relatively independent functional modules exchange data through 62256.

　　System software design

　　Since the two modules of the system are relatively independent in function, the corresponding software also includes two main modules. After the program is loaded, ADmC812 enters the normal operation of the program. After the system is initialized, it first requests DMA operation from F206 through P1.0, and after receiving the response, ADmC812 obtains 62256 control rights. At this time, ADmC812 can be made to work in different modes by configuring three special function registers ADCCON1~3. In DMA mode, the ADC can continuously convert and capture the sampled values ​​to the external RAM space without any intervention from the microprocessor. The interrupt bit ADCCON2.7 indicates the end of the DMA conversion. After the A/D conversion is completed and the sampling points reach the predetermined number, ADmC812 interrupts through the ADC, gives up control of the 62256 and notifies the DSP for data processing. Then ADmC812 enters transactional work such as display, key functions, I/O operations, and serial communication.

　　After receiving the DMA request from ADmC812, F206 enters the waiting state and gives up control of the external bus. 62256 obtains the sampling data through ADmC812. When the sampling is completed, the DSP returns from the waiting state to the normal operating state and obtains control of the bus, performs data processing, and returns the operation results to the 62256. The DMA operation process of F206 is: F206 pin / gets a valid falling edge. When the CPU transfers to the 0002H address unit, the CPU extracts the interrupt vector from the 0002H address unit and enters the interrupt service routine. After successfully testing MODE=0 Afterwards, the interrupt service routine executes an IDLE instruction, causing F206 to enter the waiting state. When a rising edge on the / pin is detected, the CPU exits the IDLE state and returns the external bus to its normal state to execute the data processing program.

　　The software is designed using C language, and programming and debugging are performed on two development systems. Using the software development tools provided by ADI, the design of the ADmC812 application can be completed quickly and efficiently, and the ADmC812 can be debugged online and downloaded through the universal serial port. F206 uses the TDS-510 development tool provided by Wenting Company for software design. Finally, ADmC812 and F206 are debugged online to complete the development of the entire software.

　　Conclusion

　　The above design scheme is suitable for application fields with large amounts of data collection, complex algorithms, and certain real-time requirements. Since the dual-CPU system does not require additional dual-port RAM, FIFO and complex control circuits, it reduces costs, simplifies the circuit, and expands the application scope of ADmC812.