Implementation of an RFID wireless communication system based on FPGA

With the rapid development of computer technology, electronic information technology is increasingly popularized in all walks of life. The traditional way of collecting logistics information is for staff to check the tickets and then input the data on the tickets into the computer. This process is time-consuming and laborious, and may cause various erroneous data due to various human errors, affecting the reliability of the collected information. Automatic identification technology uses computers for automatic identification, which increases the flexibility and accuracy of input, frees people from the complicated statistical identification work, and greatly improves the efficiency of logistics information collection. At present, the RFID application promoted by large supermarkets such as Wal-Mart and Metro has brought benefits to the retail industry, including reducing labor costs, improving the visibility of goods, reducing losses caused by out-of-stock goods, and reducing theft of goods. Its applicable processes include: real-time statistics of sales data of goods, replenishment, anti-theft, etc. This paper uses RFID technology to build a wireless communication system with FPGA chips and NRF905, and successfully realizes wireless data transmission and reception.

1 System Design

1.1 Introduction to RFID

RFID (Radio Frequency Identification) uses radio waves to read/write recording media. The distance of RFID can reach tens of centimeters to several meters, and according to the reading/writing method, thousands of bytes of information can be input. At the same time, it also has extremely high confidentiality. RFID technology is applicable to the following fields: material tracking, vehicle and shelf identification, etc., which require non-contact data collection and exchange, and are particularly applicable to occasions that require frequent changes in data content. For example, the main technology used in Hong Kong's vehicle automatic identification system, EasyPass, is RFID technology. RFID technology has also been widely used in the automatic management of identification of other items.

As shown in Figure 1, the entire architecture of this wireless system consists of a control module, an SPI module, and an antenna module. The configuration of the SPI module is completed by the control module through the Wishbone bus, and the configuration, mode conversion, and data transmission and reception of the antenna module are all completed by the control module through the SPI bus. Each part will be described below.

1.2 Antenna module (NRF905 transceiver module)

1.2.1 Introduction to NRF905

NRF905 is a single-chip RF transmitter chip launched by Nordic Company of Norway. It has an operating voltage of 1.9-3.6 V, a 32-pin QFN package, and operates in three ISM channels: 433/868/915MHz. It can automatically complete the processing of headers and CRC (cyclic redundancy check), and can automatically complete Manchester encoding/decoding by the hardware on the chip. It uses the SPI interface to communicate with the microcontroller. It is easy to configure and has low power consumption. When transmitting with an output power of -10 dBm, the current is only 11 mA, and the current is 12.5 mA in the receiving mode.

NRF905 has two working modes: ShockBurst receiving and ShockBurst sending; two power saving modes: power down and SPI programming and standby and SPI programming. The characteristic of its ShockBurst working mode is that it automatically generates preamble and CRC, which can be programmed and configured through the SPI interface. The working mode of NRF905 is set by the settings of TRX_CE, TX_EN, and PWR_UP, see Table 1.

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1.2.2 NRF905 configuration and working process

All configurations of nRF905 are done through the SPI interface. The SPI interface consists of 5 registers, and an SPI instruction is used to determine what operation to perform. The SPI interface is only active in power-down mode and standby mode.

The five registers of the SPI interface are:

(1) Status register: The register contains the data ready DR and address match AM status.

(2) RF configuration register: The register contains the configuration information of the transceiver, such as frequency and output power.

(3) Send address: The register contains the target device address, and the byte length is set by the configuration register.

(4) Send valid data: The register contains the valid Shock Burst packet data to be sent, and the byte length is set by the configuration register.

(5) Receive valid data: The register contains the received valid ShockBurst packet data, the byte length is set by the configuration register. The valid data in the register is indicated by the data ready DR.

ShoekBurst technology enables nRF905 to provide high-speed data transmission without the need for a high-speed controller for data processing or clock override. By placing high-speed signal processing related to the RF protocol into the chip, nRF905 provides an SPI interface to the application controller, and the rate is determined by the interface speed set by the microcontroller itself. nRF905 reduces the average current consumption in the application by reducing the speed of the digital application part when the RF is connected at the maximum rate through the ShockBurst working mode. In ShockBurst RX (receive) mode, the address match AM and data ready DR signals notify the controller that a valid address and data packet have been received respectively. In ShockBurst TX (transmit) mode, nRF905 automatically generates a preamble and CRC check code, and the data ready DR signal notifies the controller that the data transmission has been completed.

1.3 SPI module

1.3.1 Introduction to SPI Bus

SPI (Serial Parallel Bus) is a synchronous serial peripheral interface proposed by Motorola, which allows the CPU to communicate with various peripheral interface devices in serial mode. It uses 4 lines: serial clock line (SCK), master input/slave output line (MISO), master output/slave input line (MOSI), and low-level effective enable signal line (SS). In this way, only 3 to 4 data lines and control lines are needed to expand various I/O devices with SPI interface.

The data in SPI bus mode is transmitted in bytes (multiple bytes can be transmitted at a time), each byte is 8 bits, and each command or data block is byte-aligned (an integer multiple of 8 clocks). Data is transmitted bit by bit, with the high bit first and the low bit last. It is full-duplex communication. The data transmission speed is generally faster than the I2C bus, and the speed can reach several megabits per second. The SPI interface works in master-slave mode. This mode usually has a master device and one or more slave devices. In the wireless communication system designed in this article, the SPI bus interface module implemented by FPGA is the host, and the SPI module of NRF905 is the slave.

SPI timing mode selection:

The SPI interface has 4 different data transmission timings, which are a combination of CPOL and CPHL. CPOL is used to determine the idle level of the SCK clock signal; when CPOL=0, the idle level is low, and when CPOL=1, the idle level is high. CPHA is used to determine the sampling time, when CPHA=0, sampling is performed on the first clock edge of each cycle; when CPHA=1, sampling is performed on the second clock edge of each cycle.

Figure 2 is a timing diagram of the SPI interface of NRF905. Therefore, the SPI working mode designed in this paper is under the timing of CPOL=O, CPHA=O.

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1.3.2 SPI Hardware Design

Figure 3 is a block diagram of the SPI module in the wireless communication system of this paper. The SPI in this system is mainly composed of a clock generation module, an SPI register group, and a SPI function configuration module, and is connected to the controller through the Wishbone bus. The specific design is as follows:

Clock generation module: Since the SPI module is implemented based on FPGA, and the clock provided by the FPGA is fast (50 MHz or 100 MHz), it is not suitable for communicating with the SPI interface of NRF905 (1 Hz to 10 MHz), so it is necessary to divide the frequency to slow down the clock. However, the frequency division is completed by the SPI function configuration module. Secondly, since the SPI protocol specifies that data can be triggered on the rising edge or the falling edge, it is also necessary to identify the rising edge or the falling edge of the clock (also called the edge capture program), and this function is also completed by this module.

SPI register module: This module implements a 128-bit register group consisting of 16 8-bit registers, which means that 8 to 128 bits of serial data can be sent and received at one time through the SPI interface. The specific operation is completed by the SPI function configuration module.

SPI function configuration module: This module is equivalent to an SPI controller. It determines the clock frequency division, the number of data bits to be sent and received, and the data transmission on the rising or falling edge of the clock by configuring its registers. The configuration of these registers is completed by the control module. The following is a brief description of the configuration registers.

First, let's introduce the control register:

• Control register bit O go: whether to start sending.
• Control register bit 1 rx_negedge: whether the received data is a falling edge or a rising edge.
• Control register bit 2 tx_negedge: whether data is sent on the falling edge or the rising edge.
• Control register bits 3 to 9 char_len: the number of bits of transmitted data (since SPI is full-duplex, this is actually also the number of bits of received data).
• The 10th bit of the control register, LSB: whether to send from the high bit or the low bit.
• Control register bit 11 ie: whether to send an interrupt signal after reading and writing are completed.
• Control register bit 12 ass: whether to automatically generate chip select signal.
• Frequency divider register: spi_divider_sel.
• Status register: spi_ctrl_sel.
• Data register O: spi_tx_sel[0].
• Data register 1: spi_tx_sel[1].
• Data register 2: spi_tx_sel[2].
• Data register 3: spi_tx_sel[3].
• Chip select signal register: spi_ss_sel. [page]

1.4 Control Module

For the control module, its implementation method is to use a finite state machine based on the Verilog language, which is equivalent to controlling the SPI module to receive and send data one by one. The control module is divided into three independent parts, namely the receiving control module, the sending control module and the NRF905 configuration module. The receiving and sending control modules respectively contain the states for configuring the SPI. The design of the receiving control module is described below. Figure 4 is the state machine transition diagram synthesized by Debussy.

There are many states designed to complete wireless communication, which are relatively complex, so only the more important states are briefly explained. Idle state, complete the initialization of the port register clearing; config_div state, divide the clock (define sclk); configwb_in state, define the number of bits of data to be transmitted and whether it is sent and received on the rising edge or the falling edge, wb_inl, wb_in2, wb_in3, wb_in4, these four states are the numbers to be written to the SPI configuration through the Wishbone bus interface (each state corresponds to a register); configspi_out state, start transmitting data; done state, chip select high data transmission is completed; readeonfigreg_prel state, set the number of bits of data to be sent; readconfigreg (read register control word bit) state, read the SPI configuration read command word through the Wishbone bus interface; readconfigreg_out state, set the send/receive data bit; alldone state, chip select high to complete the configuration data reading process.

This design takes into account the correctness of the configuration verification process, so the state of reading register configuration data is specially set. Ehangemode is the receiving state. When the reception is completed (DR=1), it enters the eh-angmodee state to read the received data. Then it returns to the readeonfigreg_prel state to wait for new transmission data.

2 System Verification

The design was finally verified at the board level, and the FPGA development board and the NRF905 PCB board constituted this verification system. The FPGA chip used was Xilinx's XC2V1000, the synthesis tool used was Synplify, the tool used to view the waveform for pre-simulation and post-simulation was Modelsim, the layout and routing tool and download tool used were iMPACT integrated in ISE10.1, and the tool used to view the waveform for board-level testing was Chipseope.

Before downloading, this design was fully functionally simulated, and the SPI slave was written in Verilog to imitate the SPI interface of NRF905 to communicate with the SPI master to ensure that the pre-set functions could be completed.

Downloading is downloading the configuration file to a specific FPGA chip. The JTAG download method is used in this system, and the download tool is iMPACT, an integrated tool of Xilinx ISE. Pin binding is performed before downloading. The purpose is to constrain the input/output ports of the design to the appropriate pins of the FPGA chip, so as to facilitate its analysis and debugging and connect it to the external I/O. The following is the relevant content in the corresponding pin constraint file in this design.

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After the download is complete, connect the FPGA development board to the NRF905 PCB according to the pin binding. Figure 5 is the PCB connection diagram for wireless transceiver.

This is just one end, which is assumed to be the receiving end here, and there is another interconnected PCB board as the sending end. The PCB board on the right is the FPGA used to implement the SPI module and the control module. The small PCB board in the upper left inverted convex shape is the NRF905. The PCB board on the left connects the FPGA and the NRF905 and provides power to the NRF905.

After the system is established, the next step is the final board-level verification. Figure 6 shows the waveform obtained using Chipscope. mosi and miso are the signals on the SPI bus at the transmitting and receiving ends respectively. It can be seen from the figure that the data are basically consistent, which shows that the designed wireless communication system using FPGA to control NRF905 can work normally.

3 Conclusion

This paper implements a wireless communication system that controls NRF905 with FPGA. Through the establishment, simulation test and board-level verification of the system, it is proved that the wireless communication system can work normally, and the communication distance of the wireless system can reach 100 m, which basically meets the requirements of wireless system communication, fully demonstrating the practicality of the designed system.