FPGA high-speed hardware-in-the-loop simulator for motor controller testing

introduce

Electric motors play an important role in modern life. For safety, cost, and efficiency reasons, engineers, especially those working on hybrid electric vehicles (HEVs), often want to test motor controllers by simulating motor models in a specific real-world environment.

HEV has received extensive attention due to its advantages in economy and environment, and the motor is the core component of HEV. Especially considering that the motor and power electronic devices of HEV are large in size and high in cost; before letting the controller control these actual components, it is very necessary to use hardware-in-the-loop simulation method to test and verify the performance of the controller.

This article discusses the high-speed HIL simulator designed based on FPGA to implement motor controller testing. The figure below shows the HIL test system.

The motor drive simulator includes the DC voltage source, inverter bridge and motor. We support both permanent magnet synchronous motors (PMSM) and brushless DC motors (BLDC).

Why do we need an FPGA-based hardware-in-the-loop simulator?

Modern motor drive systems are usually driven by pulse width modulation (PWM). The following figure describes the basic concept of PWM.

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The motor controller compares the reference waveform with the triangular carrier to determine the state of the gate control signal.

When , the gate control signal of the upper power electronic device is high, and the control signal of the lower device is low

When , the gate control signal of the upper power electronic device is low, and the control signal of the lower device is high

Accurately detecting the switching moment of the gate signal is very important for the simulator to correctly generate simulation signals. Otherwise, the simulator may produce inaccurate results such as jitter, non-characteristic harmonics, or even become unstable. The figure below shows the current waveform simulation result of the PMSM motor drive.

The PWM frequency is 10 kHz. It can be seen that the simulation loop rate of 50 kHz is not enough for the simulator to detect the switching moment in time.

Therefore, accurate results cannot be obtained. Unwanted harmonic components are included in the test results, which makes the results deviate greatly from the expected values. At a cycle rate of 200 kHz, the test results are much better.

To obtain accurate results, the simulator’s sampling interval must be much smaller than the controller’s PWM cycle. Such high cycle rate applications make FPGA-based solutions ideal. Both our fixed-point PMSM model and fixed-point BLDC model can complete an update operation within 40 FPGA clock cycles.

Tip: Sometimes the desired simulation cycle rate may exceed the rate that the simulated I/O can achieve. Generally, there is no need to update the analog I/O (torque input, current output, etc.) to match the simulation cycle rate. Users can use multi-frequency programming to keep the digital I/O and simulation cycle at a high rate for accurate detection of the gate signal switching moment, while setting the analog I/O in another cycle state, and then transfer data between the two cycles with different frequencies through the FIFO.

Design Assumptions

a. Ideal switch model of power electronic devices

Power electronics are modeled as ideal switches. When the gate signal is true (high), the switch is an ideal short circuit. When the gate signal is false (low), the switch is an ideal open circuit. Ideal switch models are very suitable for system-level simulations, where we are not concerned with the parasitic effects of power electronics. In addition, ideal switch models can significantly increase simulation speed.

For the heat loss of power electronic devices, their equivalent resistance can be calculated and this resistance value can be included in the total resistance of the motor.

b. Integration method

The mathematical model of the motor is a set of differential equations. When simulating the motor drive model on the FPGA, these differential equations are actually integrated on the FPGA. The expected integration step size is very small, only on the order of a few microseconds.

Therefore, users can choose the simplest integration method, such as Euler's method, which is suitable for small step sizes. [page]

Solution flow chart

The figure below is a flowchart for creating an FPGA-based motor simulator.

In the first step, users need to collect motor parameters and raw data. Use floating-point simulation to verify whether the simulation results are consistent with the measured data. Then use fixed-point simulation to verify the fixed-point motor model to determine whether the accuracy meets the requirements and whether the output results are satisfactory. After completing the fixed-point model verification, you can enter the final deployment stage.

Meeting the Challenges of Fixed-Point Implementation

Different motors usually have very different power levels, but the range and accuracy of fixed-point data types are fixed, so it is very important to choose the right fixed-point data type, otherwise quantization errors will accumulate quickly and lead to incorrect simulation results. It is often difficult for users to adjust or calibrate all fixed-point configurations to suit their own situation. National Instruments provides the following solutions to meet these challenges.

a. Normalized system

In addition to using engineering units, electrical engineers also use normalized systems. A normalized system scales current, voltage, speed, etc. to a uniform value so that the normalized value of the operating point is close to 1.0. This characteristic of a normalized system is very suitable for fixed-point implementation. Normalization allows the fixed-point motor model to be used for a variety of different motors.

After using the normalized system, the user can select certain predefined fixed-point data types for the fixed-point motor model. The following table is a partial list of choices.

The above options all leave margins for extreme situations (such as current overload, etc.).

Determining the fixed-point data types of the above parameters can help the user select the fixed-point configuration of the internal calculation unit, such as the conversion from Idq to Iabc in the following figure.

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b. Move some of the computation to the host

The motor simulation process involves some division operations, such as . This type of operation does not involve time-varying parameters such as current, so the user does not need to update this value at each step. The user can move this division operation to the host to calculate it, avoiding the thorny problem of performing division operations in the FPGA.

Therefore, two VIs are required for the fixed-point motor model. The host VI handles some division operations and parameter conversions; the FPGA VI is used to simulate the fixed-point motor model of the target.

Case

The figure below shows the velocity and electromagnetic torque of the fixed-point PMSM model during acceleration and deceleration.

The user can observe the regenerative braking effect during the deceleration phase in the figure above. When the motor feeds energy back to the DC power source (battery), the electromagnetic torque is negative.

in conclusion

This article introduces a LabVIEW FPGA-based motor drive simulator that can be used to help users create high-speed motor drive HIL tests using NI-RIO hardware.