Design of hardware platform for speed control system based on TMS320VC33

The maglev railway test line of the Magnetic Levitation Center of the National University of Defense Technology in Changsha is the first maglev line in my country to pass the pilot evaluation and has independent intellectual property rights. The driving system of the train is networked by the S7_300 series PLC. The main control PLC processes the control commands from the driving console and transmits the processed control information to the bottom control PLC through the FDL network. The bottom control PLC controls the vehicle equipment according to the commands transmitted from the network. There is a 12-level control handle on the driving console, which controls the running status of the train. The train speed is controlled by indirectly changing the traction force by adjusting the level. The driving of the train mainly depends on the driver's experience, which increases the burden on the driver and is very easy to fatigue on short round-trip routes.

The DSP-based maglev train speed control system was proposed under the above background. After the speed control system is adopted, the driver's console no longer gives the size of the control force, but the size of the speed. The speed control platform dynamically changes the train traction according to the algorithm. The driver only needs to change the level, and the other work is done by the speed control system. This not only reduces the driver's workload, but also helps to improve the driving quality of the train. Considering that the main control PLC is not suitable for mathematical operations, we specially designed a hardware platform for the speed control system. It uses TMS320VC33 (hereinafter referred to as VC33) DSP as the core and is equipped with corresponding interfaces to achieve speed control.

1 Overall structure of speed control system

The running speed of the maglev train is very high, so the speed control system is required to have extremely high real-time processing speed. The VC33 DSP is a 32-bit floating-point processor that uses a 0.18-micron manufacturing process and is the latest generation of the C3X family. The functional structure of the VC33 is similar to that of the C31, but due to the optimization of the clock, power supply, and storage area design, it has a faster working speed (each instruction only needs 13ns to execute), lower power consumption, and integrates a larger on-chip storage area.

The dashed box in Figure 1 is the hardware platform of the speed control system. It is divided into three parts: the interface with the driving console, the DSP processor, and the interface with the PLC. Both the driving console and the PLC operate on digital I/O quantities, which use a 110V power supply voltage, while the digital I/O quantities of the DSP platform are all 3.3V~5V, so the conversion between 110V I/O quantities and 3.3VI/O quantities must be realized on the I/O interface. The detection system measures and uploads the speed and position information of the train through the CAN bus, and the main control PLC and DSP use the RS485 interface to receive it.

2 Design of digital I/O interface board

The I/O interface board (see Figure 2) uses the optocoupler chip TLP521-4 to achieve level conversion between 110V switching quantity and 3.3V switching quantity. LVT16245 is used as a latch between the DSP target board and the digital I/O conversion interface to control the direction of the data flow and also as a data driver. It is a three-state output and presents a high impedance state when not selected. The indicator light indicates the switching quantity information. It should be noted that R1 and R2 are current limiting resistors. Considering the power consumption, high-power resistors (such as 2W) should be selected.

3 Design of DSP control panel

3.1 Power Clock Circuit

Different from other members of the C3X family, VC33 uses two power supplies, 3.3V as the chip's operating voltage and 1.8V as the chip's core operating voltage. Using two power supply voltages can not only ensure the chip's ability to drive peripheral circuits, but also effectively reduce chip power consumption and heat generation. The usual power supply only provides a standard power supply voltage of 5V, so TPS767D318 is used to convert 5V to 3.3V and 1.8V. It can output 3.3V and 1.8V at the same time, and can provide a maximum current of 1A. The power clock circuit is shown in Figure 3. The diode in the figure plays the role of maintaining the output voltage difference.

VC33 DSP strengthens the role of the clock circuit, with a total of 5 pins as access pins for the clock circuit. EXTCLK connects to the external clock source, and the DSP uses the external clock as the system clock. This pin is grounded when not in use; XIN and XOUT connect to the external crystal oscillator as the reference clock source of the DSP; CLKMD0 and CLKMD1 are clock mode selection pins, which can adjust the operating frequency of the DSP based on the reference clock source. The optional clock modes are shown in Table 1.

3.2 Storage Area Circuit Design

The increased on-chip storage capacity is where VC33 is significantly superior to other members of the C3X family. VC33 has a total of 34K 32-bit storage areas, and the 24-bit address line can access a maximum of 16M storage space. Microprocessor mode and microcomputer mode define different storage space allocation methods. When in microprocessor mode, the DSP runs the program downloaded to the SRAM storage area by the emulator under the condition of emulator monitoring; when in microcomputer mode, the BOOTLOADER in the DSP downloads the program stored in ROM or FLASH to the SRAM area and starts running, and the emulator does not work at this time.

In actual applications, the on-chip storage area of ​​VC33 cannot meet the needs of running programs and storing data, so it is necessary to expand the external storage area for the system, including static SRAM area and permanent ROM area. The SRAM area is used in conjunction with the internal storage area of ​​VC33 when the system is working, as the working area of ​​the system, and the ROM area permanently stores the running program and specific parameters. When the system is powered on, the boot program reads the program and data in the ROM area into the SRAM area.

The high-speed feature of VC33 requires that the extended SRAM must have an extremely high access speed. Here, two 64K×16-bit IDT71V016 SRAMs are selected to form a 64K×32-bit off-chip storage area. Its address access time is only 12ns, which can meet the access speed requirements.

Since the system only accesses the permanent ROM when powered on and reset, the access time requirement is not too high. A 512K×16bit am29lv800b FLASH ROM is used, and its access time is 60~120ns. FLASHROM can be erased repeatedly, the data is stored for a long time, and the writing program does not require additional tools. Ruitai Innovations provides a dedicated FLASH writing program, which can also be written by yourself according to actual conditions, with good flexibility.

Figure 4 is the circuit design schematic, using G20V8B for address gating, and the address gating logic of the DSP board will be introduced in detail later. In the figure, CLKR0 is the serial port clock pin, which is used as an I/O port (can be realized by setting the serial port control register) to receive the FLASH status signal.

3.3 Digital I/O Interface Design

The digital I/O interface is used to connect to the I/O interface board to send and receive 32-bit switch control information. LVT16245 is used as the bus driver and data latch of the 32-bit data line to ensure the transmission quality of the signal. The 32-bit signal is sent and received via the 32-bit data bus, and the corresponding address selection logic controls the reading direction of the signal. Because the DSP reads data from the driving console and then sends the data to the PLC, the address selection logic must take into account the data flow direction of the I/O interface board while controlling the data direction of the LVT16245.

3.4 Serial port design

The DSP system board needs to collect speed and position information from the RS485 port. The DSP itself has serial port pins, but its transmission is synchronous and cannot be connected to the asynchronous RS485 interface. Therefore, the asynchronous communication chip TL16C550C with automatic flow control function is selected to realize the serial port communication of the DSP (see Figure 5).

TL16C550C (ACE) implements the conversion from serial port to parallel port when receiving data from peripherals or modems, and implements the conversion from parallel port to serial port when receiving data from CPU. The CPU can read the status of the chip at any time. ACE includes full modem control capabilities and processor interrupt system, which can be combined to minimize the communication connection software management.

ACE contains a baud rate generator that can divide and multiply the input clock. The rule includes a 16-times clock for the receiver. ACE has a serial port transfer rate of 1M baud, so each bit takes 1μs and one byte takes 10μs.

ACE contains 12 fully accessible registers. DSP can control the working state of ACE by reading and writing these registers. A0~A2 is used to select the register address, and D0~D7 is used to read and write the register content.

ACE can directly communicate in 9-wire mode. To improve the serial port driving capability and adapt to RS232 and RS485 standards, two additional serial port chips MAX232 and MAX485 are added to it, so that the DSP board does not need additional equipment when transmitting information through the serial port. Different serial port communication modes can be switched through jumpers.

3.5 Address allocation and selection

The storage area, digital I/O port, and serial port introduced above all need to occupy the 16M address space of DSP, so the key is to properly allocate the address and strobe pins. VC33 provides a dedicated address strobe pin STRB, which is used in conjunction with the pre-decoding pins PAGE0~PAGE3 to quickly access specific addresses. The address distribution of this system is relatively complex, and GAL20V8B is used for logical operations. Table 2 is the address space allocation table.