Analysis of galvanometer scanning laser marking system based on DSP

0 Introduction

The galvanometer scanning laser marking technology is to change the propagation direction of the laser by controlling the deflection angle of two high-speed galvanometers, and focus the laser on the workpiece surface through the F-Theata lens to mark the workpiece surface. Compared with the traditional marking technology, it has a wide range of applications (suitable for processing surfaces of different materials and shapes), no mechanical deformation of the workpiece, no pollution, fast marking speed, good repeatability, high degree of automation, etc. It has a wide range of uses in many fields such as industry, national defense, and scientific research. High-speed and high-precision galvanometer marking has become the development direction of the marking industry today.

The traditional galvanometer marking control system is connected to the single-chip control board through the serial port and parallel port ISA bus of the PC. This method has a simple interface, convenient connection, and low development cost, but due to the low transmission speed, it can no longer meet the real-time requirements of modern CNC systems. This paper makes some new explorations in laser marking control technology: using the high-speed data transmission of PCI and the high-speed data processing capability of DSP, a "PC + PCI bus + DSP control board" method is proposed for the galvanometer marking control system, thereby achieving precise control of marking control, improving control efficiency, and ensuring the real-time performance of the system. The DSP control board is the core of the entire system, which directly determines the scanning speed and scanning accuracy of the system. This paper will focus on the design of the control board.

1 DSP chip

The main chip of the DSP control board is the high-speed data processing chip TMS320C6205 of the C6000 series of Texas Instruments . This chip is a high-performance fixed-point processor with a main frequency of up to 200MHz. It can execute 8 32-bit instructions per cycle and a processing speed of up to 1600MIPS. It adopts the high-performance VLIW structure TMS320C62xTM DSP core, has 8 independent functional units, 32 32-bit general registers, provides 64K bytes of internal program RAM and 64K bytes of internal data RAM, provides 32-bit external memory seamless interface, including synchronous devices (such as SDRAM, SBSRAM, etc.), asynchronous devices (such as FLASH, SRAM, etc.) and addressable 52M bytes of external storage space, provides flexible PLL and clock generator, and can configure the multiplier value, provides PCI bus interface that complies with PCI 2.2 specification, directly realizes the bridge function between chip and PCI bus, provides two 32-bit timers, and provides JTAG boundary scan interface for online debugging. Using this chip can realize high-speed data processing, ensure the real-time operation of the system, and because it has PCI bridge function, it provides interface with PCI bus, which is economical and reliable. 2 Hardware Design 2.1 Block Diagram As shown in Figure 1, the hardware block diagram of the system is shown. The DSP control board is connected to the PC through the PCI bus to achieve high-speed communication. The DSP processing module is the main control module, and the TMS320C6205 chip with a main frequency of 200MHz is used as the main control chip. The DSP processing module makes full use of the fast computing power and high-precision timer of the C6000 series DSP to ensure that the galvanometer marking machine can mark at a uniform speed and high speed, which is impossible for a PC. The peripheral circuit of the DSP includes a storage module, reset control, power control, clock system, JTAG port, digital-to-analog conversion module, CPLD logic control module, and optoelectronic isolation module. The storage module includes a FLASH module and an SDRAM module. FLASH is used to store the system startup code and software code, and SDRAM is used to provide additional storage space required for software operation. The DSP control board outputs two analog quantities to control the movement of the two galvanometers, outputs a Q switch control signal to control the switching light of the laser, and inputs/outputs 16 optoelectronic isolation signals for function expansion. 2.2 Communication between PC and DSP PCI bus is a local bus that is not attached to a specific processor. Structurally, PCI is a first-level bus inserted between the CPU and the original system bus. A bridge circuit is used to manage this layer and implement the interface between the upper and lower layers to coordinate data transmission. The manager provides signal buffering, enabling it to support 10 peripherals and maintain high performance at high clock frequencies. The PCI bus also supports bus master technology, allowing intelligent devices to obtain bus control when needed to accelerate data transmission. Compared with the ISA bus, the PCI bus has the advantages of fast transmission speed and large transmission volume. This system uses TMS320C6205, which has a PCI bus bridge function that complies with the PCI2.2 specification. Developers are exempted from the hardware and software implementation of the PCI protocol, which brings convenience to system design, shortens the development cycle, and saves development costs. Developers only need to directly connect the bus signal on the PCI slot with the relevant PCI bus signal on the DSP chip. The DSP control board with "gold finger" can be directly inserted into the PCI card slot of the PC to realize the communication between the PC and the DSP. The PCI device can access all internal RAM space, peripherals and external memory space. The PCI bus width used by the DSP control board is 32 (3.3V), the bus frequency is 33MHz, and the transmission rate is 33×32/4MB/s = 132MB/s. This transmission rate provides a guarantee for the high-speed operation of the entire system. 2.3 CPLD logic control The logic control of the entire high-speed system is realized by a high-speed CPLD chip. The MAX7128E chip of ALTERA is selected for implementation. The programmable logic gates are 2500, the number of macro units is 128, the number of logic array blocks is 8, the user can define 100 I/O pins, and the pin-to-pin delay is 5ns. The MAX7000 series devices can be programmed through a programmer or online. This design uses online programming (ISP). ISP allows for quick and easy reprogramming during the design and development process, simplifies the manufacturing process, and allows the device to be assembled on the printed circuit board before programming. In the system design, LED signal lights, FLASH, DA chips, 16-channel I/O optoelectronic isolation interfaces, analog switches, Q switches, PWM outputs, and software reset controls all use the address of the CE1 space. In order to prevent these devices from interfering with each other, the input address must be decoded. By judging the PA[2:6] and PA[16:21] input to the CPLD, it is possible to know the address area that the DSP is accessing, and perform address decoding of the CE1 space to generate corresponding control signals to achieve logic control and timing control. The high addresses of the registers built on the CPLD are all the same, named dsp_reg_addr, and are composed of Pa16~21. If Pa16~21 is set to "111000", it means the address 0x0178xxxx. The low address is composed of Pa2~6, which addresses 10 registers. The address correspondence is shown in Table 1. Table 1 Address allocation table [page]

2.4 Digital-to-analog conversion module

The digital-to-analog conversion module converts the digital signal processed by DSP into an analog signal to control the deflection of the two galvanometers. As the requirements for marking accuracy are getting higher and higher, the traditional 8-bit digital-to-analog converter can no longer meet the needs of users. Therefore, this system uses ADI's 16-bit high-precision digital-to-analog converter AD669 chip, as shown in Figure 2. AD669 has a 16-bit parallel input and a secondary data cache structure. In the design, the /L1 signal is directly grounded and set to be valid, and the first-level cache and the second-level cache are controlled by controlling the /CS and LDAC signals respectively. The voltage range of the control galvanometer signal is -10V~+10V. Taking the label with a size of 100mm×100mm as an example, the accuracy can reach 100mm/216=0.0015mm, corresponding to a minimum output voltage of 0.00031V.



It was found through experiments that when powered on, the output of the AD669 chip is an uncontrollable quantity, which will cause the galvanometer to deflect at the moment of power-on. If the deflection amplitude is too large, long-term use will cause the galvanometer to break. In order to protect the galvanometer, an analog switch circuit can be designed to control the output of the AD669 chip when it is powered on, so that it is 0V. The author puts the analog switch at the reference voltage input end of the AD669 chip, and controls the analog switch through CPLD to control the presence or absence of the reference voltage, thereby ensuring that the galvanometer does not deflect when powered on.

3 PCB design

The control board uses a high-speed DSP processing chip with a main frequency of 200MHz. In the high-speed signal system, there are EMC problems, which will affect the performance of the system. In order to design a stable control board with good anti-interference performance, the following measures are taken

1. Reasonable arrangement of board layers

The control board is a six-layer board, and the board layer design is (from top to bottom in order) signal layer-ground layer-power layer-signal layer-ground layer-signal layer. This board layer structure arrangement makes each signal layer and power layer close to a ground layer, providing a shorter return path for the signal.

2. Processing of clock signal lines

Half of the PCI clock signal needs to be enhanced by reflected waves. Therefore, the length of the clock signal CLK line is approximately 2500 mil, which is achieved by serpentine lines (this point is clearly stipulated in the routing requirements of the PCI2.2 specification). For DSP chips, the crystal oscillator circuit should be as close to the DSP chip as possible, and the clock signal should be as short as possible.

3. Processing of SDRAM related signal lines

The operating frequency of SDRAM is 100MHz. At high frequencies, the transmission time of the signal is directly related to the length of the signal line, and this problem cannot be ignored. Therefore, the data line and address line of SDRAM should be routed with equal length to ensure the quality of signal transmission. In addition, crosstalk and ringing problems are also very easy to occur at high frequencies. For the control signals and data and address bus signals of the SDRAM and DSP interfaces, matching resistors are connected in series at the source end to improve the quality of signal transmission and ensure that SDRAM can work normally at high frequencies.

4. Isolation of digital

and analog circuits There are digital circuits and analog circuits on the control board. When laying out, the isolation of digital and analog circuits must be considered. Try to layout the digital circuits and analog circuits in blocks to avoid digital signal routing crossing the analog circuit area to prevent mutual interference between the two circuits. In addition, the digital circuit and the analog circuit are grounded at one point through a 0 ohm resistor.

5. Use of capacitors

Place a 1.01uF decoupling capacitor next to the power pin of each digital chip.

4 Summary

This system combines the high-speed PCI bus with the C6000 high-speed DSP processor, equipped with a high-precision digital-to-analog conversion module, to achieve a high-speed and high-precision control system, and successfully applied it to the galvanometer laser marking system. The system makes full use of the high-speed processing capability of the DSP and the internal high-precision timer, sharing the real-time tasks of the PC, thereby realizing the complementary advantages of the PC and the DSP control board, realizing real-time marking, and ensuring the uniformity of the marking quality. This article also gives the points to note in the PCB design stage of the DSP control board. The board has been put into use in actual production and has good stability and anti-interference.