Using CPLD and Flash to implement FPGA configuration

Electronic Design Automation (EDA) refers to the process of electronic product automation design that uses computers as working platforms, EDA software as development environment, hardware description language as design language, programmable logic devices (PLD) as experimental carriers (including CPLD, FPGA, EPLD, etc.), and integrated circuit chips as target devices. This process has been widely used in the design of electronic circuits and systems and product development, and has gradually replaced the traditional manual hardware circuit design method. The designed system has the advantages of small size, light weight, low power consumption, fast speed, low price, high reliability, and short design cycle. A fully functional EDA design software plus a programmable logic chip with ordinary functions can form an electronic system that previously required hundreds of integrated circuits.

Commonly used programmable logic devices include CPLD (Complex Programmable Logic Device) and FPGA (Field Programmable Gate Array). Commonly used EDA software includes hardware description languages ​​such as VHDL, Verilog HDL, and ABEL. Among them, VHDL, as the IEEE's industrial standard hardware description language, is supported by many EDA tool manufacturers and has become the de facto universal hardware description language in the field of electronic engineering.

The physical implementation of the programmable part of Xilinx and Ahera's FPGA is RAM. Its biggest advantage is that it can be repeatedly programmed, but its disadvantage is volatility. Therefore, after each power-on, the processor needs to download the user-designed FPGA configuration file from the external memory to the FPGA. There are three ways to download and update the FPGA configuration file from the external memory:

(1) JTAG port download method

Put the configuration file in a host computer, and connect the host computer to the JTAG port hardware on the board through a dedicated line. In this way, each download requires hardware operation, so it is only suitable for the development and debugging stage, and cannot be used when the device is working on site.

(2) Off-chip serial PROM download method

Place one or more serial PROMs (determined by the capacity of the FPGA) around each FPGA. When the system is powered on, the FPGA configuration file is automatically downloaded from the PROM to the FPGA. This method is also the method that companies such as Xilinx and A1tera focus on, and is suitable for relatively stable systems. However, with the increase in the density of FPGA chips, serial PROMs can no longer adapt to the configuration of large-capacity, high-density FPGAs. The addressing method required by large-capacity parallel PROMs cannot be directly interfaced with the FPGA. When the FPGA configuration file in the system needs to be upgraded, the chassis must be opened, and the configuration file in the PROM must be updated first through the JTAG port, and then the system must be restarted to download the updated configuration file from the PROM to the FPGA. Only in this way can the FPGA configuration file be updated once.

Both of the above solutions have the disadvantage that hardware operations must be performed (opening the chassis and using the host through the JTAG port), and professional software must be installed on the host to complete the update of the FPGA configuration file.

(3) Processor controls Flash download mode

Based on the manuals of Xilinx and Altra and previous work experience, this paper proposes and completes a new way to download and update FPGA configuration files. This method is suitable for systems that support network communication. Every time the system starts, the processor reads the FPGA configuration file from the Flash and downloads it to the FPGA. That is, when the FPGA configuration file needs to be upgraded, the configuration file is sent to the processor through the network, and the processor updates the Flash in the system. When the Flash content is updated, the processor controls the automatic download of the configuration file to the FPGA. In this way, without any hardware actions and professional software, only regular software operations are required to update the FPGA configuration file. However, since Flash is a parallel data line, a CPLD is required to convert the data read from the Flash into serial data and output it to the FPGA. [page]

1 FPGA download configuration mode

There are five download modes for FPGA configuration files: master serial mode (masterserial), slave serial mode (slave serial), master parallel mode (master selectMAP), slave parallel mode (slave selectMAP) and JTAG mode. Among them, JTAG mode is used in the development and debugging stage. In order to facilitate debugging in the development and design stage, this core router design directly makes the JTAG port on the signal processing board.

The biggest difference between the master and slave modes is that the download synchronization clock (CCLK) of the master mode is provided by the FPGA; the download synchronization clock (CCLK) of the slave mode is provided by an external clock source or an external control signal. The master mode has much stricter requirements on download timing than the slave mode. Therefore, from the perspective of the processor's easy control of the download process, it is more appropriate to choose to use the slave serial mode or the slave parallel mode. This design uses the slave serial mode for FPGA configuration. The slave serial mode pin description is shown in Table 1.

The slave configuration timing diagram is shown in Figure 1. TPROGRAM is the reset time of the configuration logic. For the Xilinx VIRTEXE and VIRTEX2 series, the minimum should be greater than 300ns. TPL is the reset delay time, indicating the continuation of the configuration logic reset. For the VIRTEXE series, when the reset signal PROG becomes high, INIT immediately becomes high, and the configuration logic can receive the configuration data stream; for the VIRTEX2 series, TPL has a minimum delay of 500ns. TICCK is the output delay of the configuration clock CCLK.

When PROG is valid (resetting the configuration logic), the FPGA will set INIT and DONE low; when PROG becomes high, INIT will delay for a period of time to indicate the continuation of the reset state. Continuing to set INIT low can delay the configuration. When the FPGA is receiving configuration data, INIT becomes low, indicating that the CRC check is wrong. When all data is configured, if the configuration is correct, DONE will become high. After that, the FPGA starts the startup sequence, and continuing to set DONE low can delay the startup. [page]

2 Specific design

The National 863 Project High-Performance IPv6 Core Router undertaken by the National Digital Switching System Engineering Technology Research Center uses an Intel E28F128J3A150 16-bit Flash as BootFlash to power on the PowerPC2860 (MPC860) processor to download and update the configuration. Its extra storage space can fully store the configuration files required by the FPGA. After power-on reset and system startup, the processor cooperates with a XilinxXC95288XL CPLD to control the FPGA configuration file to be downloaded from the Flash to the FPGA to complete the configuration of the FPGA. The 860 processor supports network functions. When the configuration file needs to be updated, the new configuration file can be sent to the processor through the network, and then the processor updates the Flash in the system. The specific circuit design structure of using the XC95288CPLD to configure the FPGA is shown in Figure 2.

In Figure 2, the main function of the CPLD is to convert the data read from the Flash into serial output and then increment the address. The CCLK signal is generated by the CPU clock. The PROG signal is generated by the address data output by the CPU through the decoding module. The XC95288C PLD logic structure is shown in Figure 3.

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The specific implementation of each functional module is introduced below:

(1) Data conversion to serial output function module: A right shift register is used. After the parallel data DIN[0:15] from the 16-bit Flash is loaded into the shift register, it is serially output from DOUT to the FPGA.

(2) Address increment function module: This function is completed by two counters. Since Flash is a 16-bit parallel data port, the function of the first counter is to increase by 1 every 16 bits, and the function of the second counter is to increase the Flash address. When the 16-bit data of the shift register are all output to the FPGA, the output port CNT[0:3] of the first counter is all "1", and the second counter is incremented by 1 through the "AND gate" logic. Intel E28F128J3A150 Flash is 16MB, requiring a total of 25 address lines. Since Flash is 16 bits, ADD[31] is not connected. Therefore, the second counter is connected to the address line ADD[7:30] to complete the increment of the Flash address.

(3) CCLK signal generation module: The clock signal from the CPU outputs the data signal DOUT, and generates CCLK after a half-cycle delay through a "NOT gate" logic. CCLK then sends the data on DOUT to the FPGA. In this way, the timing of reading and writing DOUT data is separated to avoid conflicts.

(4) PROG signal generation module: When the FPGA program needs to be downloaded, the CPU generates an address signal ADD[0:30], which is decoded by the decoder to generate the PROG control signal. This address is set by the user.

The above modules are described in VHDL language. The data conversion to serial output function module is the core part, which can realize the serial output of parallel data.

This article introduces a method for downloading and updating FPGA configuration files using CPLD and Flash in a processor. Compared with the traditional JTAG or PROM serial download configuration method, this method is flexible and convenient for updating configuration files, easy to operate, and suitable for downloading large-capacity FPGAs. This method can update the FPGA configuration program at any time without opening the chassis, which is particularly suitable for system designs that require continuous updates and has a broad application prospect.