Development of Gasoline Engine Ignition Parameters Measuring Instrument Based on CPLD

Ignition parameters are one of the most important factors affecting the performance of gasoline engines. The main ignition parameters of gasoline engines are: ignition advance angle, ignition energy, ignition voltage and ignition current. By measuring, studying and optimizing these parameters, the performance of the engine can be improved, fuel consumption can be reduced, the emission of harmful gases can be reduced, and the quality of ambient air can be improved. As for the current ignition parameter measurement equipment at home and abroad, there are generally disadvantages such as large size, high price, poor anti-interference ability, and even some use oscilloscopes for observation, and the human-computer dialogue interface is not friendly enough. Since the spark plug discharge time is about 200 to 500 μs, the rise time of the ignition voltage is only a few to a dozen μs. In order to ensure the measurement accuracy, the sampling frequency is required to be above 10MHz. This rate is difficult for the fastest single-chip microcomputer at present. Therefore, how to effectively realize ultra-high-speed data acquisition has become the technical key to solving the problem. At the same time, it is another difficult problem to achieve reliable information exchange between the high-speed data acquisition device and the low-speed control circuit. This measuring instrument uses CPLD as a high-speed acquisition device and AT89C52 as a controller to cleverly solve this problem.

1 Measurement principle and method of gasoline engine ignition parameters

The principle block diagram of the gasoline engine ignition parameter measurement circuit is shown in Figure 1. The trigger signal is the signal sent by the magneto position sensor (electromagnetic induction coil), and the ignition signal is the output signal of the sensor coil on the ignition wire. These two signals are shaped by the conditioning circuit to control the start and stop of the CPLD counter. The speed and ignition advance angle can be calculated according to the count value. The secondary voltage and current signals of the ignition coil are adjusted to the input range of the high-speed A/D through a voltage divider, a shunt, and a power amplifier. The high-speed A/D converts it, and the result is latched by the CPLD and stored in the high-speed static memory SRAM through the CPLD. The entire measurement circuit works under the control of the CPU. After power-on, the CPU first configures the CPLD. After the CPLD is initialized, the entire circuit enters the working state. The sampling frequency of the circuit is output by the clock synthesis chip, and the measurement result is obtained through the CPLD and displayed on the LCD after being processed by the CPU.

1.1 Design of high-speed data acquisition circuit

The high-speed data acquisition circuit consists of a high-speed A/D converter AD9051, a complex programmable logic device (CPLD) EPF10K10, and a high-speed static memory (SRAM) CY7C1021, as shown in Figure 2. AD9051 converts the conditioned voltage and current signals into ten-bit digital outputs, and ORv and ORi are signals that the voltage and current amplitudes exceed the input range. When Fout has a pulse output, AD9051 performs the conversion, otherwise it stops working. In the signal acquisition circuit, the role of CPLD is: (1) When the SMEN signal is enabled, after the SMST (ignition signal) signal arrives, the output Fout starts the A/D converter; (2) latches the output result of AD9051; (3) outputs the data storage address through the address generator, and generates a write signal (WR) to write the latched data into the SRAM.

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1.2 Design of control circuit

The core of the control circuit is AT89C52, as shown in Figure 3. The tasks to be completed by the control circuit are: (1) After power-on, complete the configuration loading of CPLD. There are 4 loading modes in the FLEX10K series. Here, the active serial mode is adopted. The AT89C52 pin P1.5 controls the CPLD and the serial EPROM (27E512) with the configuration data written to complete the configuration. (2) Complete the control of the sampling frequency. The AT89C52 controls the time synthesis chip MC12429 to achieve this. Its output frequency is 25~400MHz. Before each sampling, the user can manually input the sampling frequency. The AT89C52 P0.0~P0.7 pins output the value of M[8..1], and the P1.0 pin outputs a signal from low to high to latch this value. (3) Control the enable of A/D conversion. When the frequency is set, the user presses the sampling key, and the AT89C52 P1.1 outputs the sampling enable signal SMEN. When the sampling start signal SMST arrives, sampling begins. (4) Communication with CPLD. In Figure 3, P0.0 to P0.7 of AT89C52 are connected to the 8 I/O pins of CPLD to realize data communication between AT89C52 and CPLD. The control signals between them include the data reading clock signal RDCK (P1.2), the input/output control signal I/O (P1.3), the CPLD selection signal PLDCE (P1.4) and the interrupt signal INT (INT0) issued by CPLD.

1.3 Interface between high-speed collector and low-speed controller

In order for CPLD to complete the corresponding functions under the control of AT89C52, a certain signal connection must be established between the two so that CPLD can identify the commands issued by AT89C52 and perform the corresponding tasks. The functions to be realized by the communication between CPLD and CPU of this measuring instrument are: determination of sampling frequency, reading of sampling results, and reading of status information. The encoding of AT89C52 input data is shown in Table 1. The status information includes: three key status bits (0-pressed, 1-not pressed), whether the two AD inputs are out of range status bits (0-out of range, 1-not out of range), and one sampling status bit (0-sampling completed, 1-sampling in progress or not started).

Table 1 Communication code between CPLD and AT89C52

D7 D6 D5 D4 D3 D2 D1 D0 Meaning

XXXXXX 0 0 1-way

XXXXXX 0 1 Two-way

XXXXXX 1 0 Four-way

XXXXXX 1 1 Eighth Frequency

0 0 0 0 XXXX Read status information

0 0 0 1 XXXX Read the lower 8 bits of the ignition boost front angle

0 0 1 0 XXXX Read the second lower 8 bits of the ignition advance angle

0 0 1 1 XXXX Read the high 7 bits of the ignition advance angle

0 1 0 0 XXXX Read the lower 8 bits of the rotation speed

0 1 0 1 XXXX Read the second lower 8 bits of the rotation speed

0 1 1 0 XXXX Read the third lower 8 bits of the speed

0 1 1 1 XXXX Read the high 2 bits of the rotation speed

1 0 0 0 XXXX Read current lower 8 bits

1 0 0 1 XXXX Read current high 2 bits [page]

2 Control Program Design

In order to display the working status of the ignition system in real time, the control circuit obtains the count value of the speed and ignition advance angle from the CPLD by query. The ignition voltage and current data are obtained by interruption, that is, after sampling and A/D conversion, the CPLD sends an interrupt to the control circuit, and the control circuit obtains data from the SRAM through the CPLD.

2.1 Design of the main program

After the control circuit is powered on or reset, AT89C52 starts to execute the main program, as shown in the flowchart in Figure 4. After the CPLD is powered on and before the configuration is completed, the CONF_DONE (as shown in Figure 3) pin is pulled down to a low level by the CPLD. Once the CPLD is successfully configured, the CONF_DONE pin is released by the CPLD and connected to a high level by the pull-up resistor. Therefore, after the control circuit is powered on or reset, as long as the CONF_DONE pin is found to be at a low level, the CPLD is configured. The initialization tasks are the initialization of special function registers, the clearing and setting of triggers in the CPLD, the setting of the default sampling frequency, and the initial setting of the LCD.

2.2 Design of interrupt program

This control circuit only uses the AT89C52 interrupt INT0, and then determines the type of interrupt in the interrupt program. There are three interrupt sources: AD input out of range interrupt, Buffer Full interrupt and key interrupt. The priority order of these three interrupts is:

A/D input out of range interrupt > Buffer Full interrupt > Key interrupt. Figure 5 is the interrupt program flow chart. After AT89C52 responds to the interrupt, it reads the status information from the CPLD and judges it in order of interrupt priority. If it is an AD input out of range interrupt, it means that the signal conditioning circuit parameters are improperly selected or there is unexpected interference superposition at this point. At this time, an alarm is displayed on the LCD and the data collection is terminated, and the sampled data is invalid. If it is a Buffer Full interrupt, the result of the A/D conversion needs to be taken out of the SRAM, calculated and displayed. If it is a key interrupt, it is necessary to determine which key is pressed, and to obtain the meaning of the key in the current state, and then complete the corresponding function.

It should be noted that the ignition energy is obtained by integrating (product-sum operation) the sampled voltage and current data within the spark duration.

This measuring instrument creatively uses CPLD devices and technologies to successfully achieve high-speed data acquisition, greatly reducing the number of integrated chips, reducing development costs, enhancing anti-interference capabilities, and greatly reducing the size of the measuring instrument, making it more portable. Compared with the existing ignition parameter measurement system, it is more suitable for quality identification in the production process, research and development of gasoline engines, and fault diagnosis in maintenance services, and therefore has a very broad application prospect.