Can domestically produced chips for smart cars break through technological barriers?

▲Estimation of the market size of China's smart cockpit equipped with heterogeneous SOC

05

High technical barriers
Differentiated services cut into independent brands
The design and manufacture of high-computing power SOC chips have a very high threshold, and must comprehensively consider performance, power consumption, cost, and vehicle safety.
▲Core design indicators of automotive AI chips
(1) Heterogeneous, multi-core SOC design and optimization capabilities directly determine the performance, reliability, and safety of high-computing power chips. There are two major technical difficulties. On the one hand, we need to understand customer needs, that is, to have a deep understanding of AI algorithms, especially the neural networks used behind them. Therefore, it is necessary to have a forward-looking understanding of new AI algorithms. Otherwise, when the chip is developed, it will be found that the algorithm is not compatible with the hardware architecture, which will greatly reduce the efficiency of the chip.
Autonomous driving is a high-level artificial intelligence. Compared with fields such as face and voice recognition and big data analysis, it has higher requirements for safety and real-time performance. In addition, since driving requires the participation of humans, it requires higher cognitive and reasoning capabilities. In addition, it is necessary to have a sufficient understanding of supply, that is, the cores inside the SOC chip, such as CPU, ISP, DSP, etc., can be obtained through IP licensing. Only by deeply understanding various IPs can we design good chips.
(2) Performance/power ratio is a key indicator for evaluating AI chips, and startups must have sufficient funds to carry out advanced process tape-out. The peak processing power per watt in each new generation of SOC is gradually increasing: Nvidia's Drive Orin can achieve a performance of 3.6TOPS/watt, which is a significant improvement over its older generation Xavier's 1.1TOPS/watt. Mobileye's EyeQ4 can also rise from 0.83TOPS/watt to 1.6TOPS/watt, and may exceed 1.76TOPS/watt in the upcoming Ultra version. Tesla has achieved 2.0TOPS/watt in HW3.0 in 2019, and expects more substantial improvements in the next generation HW4.0 platform. Ways to continuously improve the performance of AI chips include: a. Continuously optimize the SOC architecture.
For example, introduce more powerful ASIC chips - neural network accelerators (NNAs), NPUs or DLAs; b. Use more advanced chip manufacturing technology to effectively reduce overall power consumption. According to IBS estimates, the cost of developing a chip, including IP licensing, EDA (electronic design automation) software, R&D, tape out (final design process), packaging and testing costs, is $106 million for the 16nm technology node; $298 million for the 7nm technology node; and $542 million for the 5nm technology node. Therefore, whether there is sufficient funding for advanced process tape-out and whether the production capacity of advanced processes can be obtained are also key factors in whether large-scale mass production can be achieved.
(3) A series of stringent automotive certifications such as functional safety process, automotive reliability certification, and ASPICE software certification need to be overcome one by one. It takes about 2 years from chip function definition to tape-out/packaging test completion. If the early automotive chips do not involve functional safety, then this process can be accelerated. However, it takes about 1.5 to 2 years from chip testing to mass production. This link is essential because it involves functional safety certifications such as AECQ100, ISO 26262, summer and winter certification, and first-level software certification.
SOC chips are mostly heterogeneous designs, including different computing units such as GPU, CPU, acceleration core, NPU, DPU, ISP, etc. Generally speaking, chips cannot simply evaluate computing power, but also need to take into account chip bandwidth, peripherals, memory, energy efficiency, cost, etc. At the same time, in chip design, the configuration of heterogeneous IP is very important. Autonomous driving SOC chip manufacturers have continuously strengthened core IP research and development to maintain key competitiveness:
from Mobileye EyeQ3, which used black box solutions in the early days, to the more open Nvidia Drive platform, and now to the self-developed NPU chips. Tesla tightly couples chips and algorithms. Although Tesla's chip computing power is not the highest at present, its integration of software and hardware is more efficient than other OEM solutions.
It is more useful for chips to calculate faster than to have greater computing power. We can take the neurons of humans and animals as an example. For example, elephants have 257 billion neurons, while the human brain has only 86 billion neurons, but its IQ limit is only equivalent to that of a four or five-year-old human child. Similarly, as the brain of autonomous driving, the chip must not only look at the hardware stacking. The architecture design and
the operation mode of the algorithm will affect the final actual performance of the chip.
FPS (Frequency Per Second) can better reflect the real computing performance of AI chips, and this indicator has begun to be used by leading autonomous driving manufacturers. Musk mentioned in 2019 that the computing power of the FSD chip is 3 times that of NVIDIA DrivePX2; when performing autonomous driving tasks, its FPS is 21 times that of the latter.
Compared with NVIDIA Orin, although the computing power of 128TOPS of Horizon J5 is only half of that of NVIDIA, its FPS is better when performing autonomous driving tasks. Higher FPS can achieve faster perception and lower latency, which means higher safety and faster usage efficiency.
Mobileye is the main founder and leader of automotive ADAS technology in the past 20 years. As of the end of 2021, Mobileye has sold 28.1 million EYEQ chips (including algorithm solutions), with a market share of approximately 70% in L2+ solutions. Mobileye is committed to using monocular vision to solve ranging problems in three-dimensional environments. Since the founding of the company, Mobileye has won many firsts in the field of visual assisted driving and provided assisted driving technologies including pedestrian detection, lane keeping and adaptive cruise.
In the past 20 years, Mobileye has launched a series of solutions consisting of algorithms + EyeQ series chips based on visual perception technology, which can help automakers achieve various functions from L0 collision warning, to L1 AEB emergency braking, ACC adaptive cruise, to L2 self-lane keeping, automatic brake assist and automatic parking.
However, as technology giants such as Google, Apple, Baidu, Huawei, Didi, and Tesla, as well as a number of autonomous driving startups, have begun to use deep learning algorithms to develop a new generation of L4 autonomous driving technology, the L2 systems installed in mass-produced vehicles are increasingly aligned with the technical architecture of L4 autonomous driving. So Tesla replaced Mobileye with the FSD chip, and Ideal switched from EyeQ4 to Horizon Journey 3.
Among the new models that will be launched in 2022 and later, especially smart electric vehicles, almost all of them have chosen autonomous driving chips from technology giants such as NVIDIA, Qualcomm and Huawei. Currently, the only models known to use Mobileye's latest generation of EyeQ5 chips in the world are Zeekr 001 and BMW iX; and BMW, as Mobileye's largest customer, announced that it would choose Qualcomm for the autonomous driving SOC solutions of other models in the future.
Horizon has listed a table of current chip manufacturers according to the degree of openness. The four modes of openness from low to high are Mobileye, NVIDIA, Horizon Together OS, and BPU authorization. Horizon can flexibly choose the latter three modes according to the needs of downstream customers, and gradually expand its influence in the field of autonomous driving with its open ecosystem:
An open ecosystem is the first step for domestic manufacturers to catch up with NVIDIA, but the key is to build a good software system, tool chain, and a user ecosystem that can support continuous evolution and iteration. The tool chain plays an important role in the autonomous driving software ecosystem, and its maturity determines the efficiency of the entire system development. The leading SOC chip manufacturers have gradually polished and improved the tool chain by cooperating with many downstream customers to strengthen their own barriers:
Horizon provides a whole vehicle intelligent development platform, which not only includes AI chips, but also includes software stacks, Tiangong Kaiwu AI tool chain and Eddie AI development platform. Horizon provides development tools on the terminal and training in the cloud, including data management and simulation platform tools, forming a complete development platform with Tiangong Kaiwu to accelerate the development of various solutions for intelligent driving, intelligent interaction, in-car entertainment applications, etc.
Huawei's intelligent driving computing platform MDC integrates Huawei's self-developed CPU, AI chips and other control chips, and through the underlying software and hardware integrated tuning, the overall performance reaches the industry-leading level. In addition, Huawei MDC also has a complete test platform and tool chain, providing a full-stack solution for the development of MDC.
Since 2021, multiple factors have brought opportunities to domestic automotive chip suppliers on the one hand, and on the other hand, OEMs have begun to pay attention to the position of automotive chips in the industrial chain. In the past division of labor in the industrial chain, automotive chips, as traditional Tier 2 manufacturers, did not directly connect with OEMs; but affected by the chip shortage and in order to accelerate the intelligent transformation of major automakers, automotive chip manufacturers began to cooperate directly with OEMs for supporting research and development, and the voice of automotive chips in the industrial chain has increased.
Service attitude refers to how Tier-1 will implement cooperation after reaching a cooperation with the car company, such as whether it will send an engineering team to the site, whether it has a timely response speed, whether it can provide differentiated/customized services, and whether it has the ability/resources/to do after-sales.
Automotive chip manufacturers, which were originally in the TIER2 link, have achieved comprehensive integration of chips, system software, and functional software by strengthening the collaborative development capabilities of software and hardware, creating an in-vehicle intelligent computing platform that is compatible with the diverse needs of the upstream and downstream of the industrial chain, and will leap to the core position of the industry in the era of intelligent networking.