How to use Xilinx software for FPGA system design

Solution: When planning the initial system for FPGA design, we need to divide modules and define module interfaces. Usually, we can only design on paper. Although we can write freely on paper, the inconvenience of drawing on paper is that if a module is greatly changed, there is often not enough free paper, so we have to draw it again on a new blank paper.

Question: Can we use software for system planning?

Solution: The answer is yes. The following is an example using ISE 7.1:

1) Draw an empty module and define only the ports - Create a new Schematic, select Tools -> Symbol

Wizard, in which you can define the Symbol name and port properties. After completion, a Symbol in sym format is generated.

2) Add the Symbol to the schematic -

On the Schematic Symbol page, select Categories as the project folder, and you will see the newly created Symbol in the Symbols list. Add it to the schematic.

3) Repeat steps 1-2 to create all symbols and connect ports.

4) If you need to modify the Symbol, you can modify it directly in the sym file - you can right-click -> Add -> Pin, etc. to add it, or you can copy an existing Pin and then change the PinName. However, in ISE7.1, changing the copied PinName will also change the original PinName. The solution is to open the sym file with a TextEditor such as UltraEditor and modify it in it. The sym file format is easy to understand. After changing the Symbol port, you need to Update Schematic. After clicking on the Schematic, the Update dialog box will pop up automatically.

5) Generate the HDL file corresponding to the schematic - Click the sch file in the "Sources in Project" list and select "View HDL Functional Model" in the "Process" window. This will automatically generate the HDL file corresponding to the Schematic, which instantiates the above modules. To change the HDL file type, you can change the "Generated Simulation Language" property in the Project properties.

6) Generate HDL file corresponding to Symbol - When opening a sym file, select Tools -> Generate HDL Template from Symbol. You can choose to generate VHDL or Verilog file.

7) Write the content of each module.

Summary: Although I personally prefer to use HDL for design, it is very convenient to use this schematic method for top-down design in the early stage of design. First, it enhances the maintainability and readability of the design, making modification and dissemination more convenient; second, because it can automatically generate HDL code, it also simplifies the operation of the next step of design.

Advice: Several problems encountered during use, I hope Xilinx can solve them in the future

1) When editing a Symbol, changing the copied PinName will also change the original PinName

2) Symbol Wizard can add a bus, just name the Pin A (4:0)

3) You can only change the color in Pereference, but not the color of a specific connection to distinguish between control lines and data paths