FPGA Design of Ground Interrogation Encoder for Secondary Surveillance Radar of Air Traffic Control

introduction

With the development of aviation, the increase in air traffic has made the role of air traffic management system very important. Air traffic controllers use radar to provide control services for identified aircraft, and can see the information parameters of the aircraft on the radar screen. In the air traffic control system, conventional mode and S mode technology are used for monitoring functions, based on independent addressing and selective inquiry. Information exchange is achieved by pulse encoding the uplink inquiry content and the downlink response content. The encoder is the center of the entire radar, which is used to generate the whole machine synchronization signal and the inquiry signal. Therefore, the pulse coding signal processing technology of the interrogator encoder with high performance is crucial. At the same time, strict requirements are put forward for the real-time processing of radar signals, and the processing of the response signal is completed within milliseconds, the target identification is completed, and the information parameters of the target aircraft are given; at the same time, the strict requirements on equipment size and power consumption make the signal processing equipment must develop towards miniaturization, intelligence, and programmability, and the signal processing system is required to have high reliability and system upgrade needs.

Field programmable logic devices and related technologies are the product of the rapid development of contemporary microelectronics technology. FPGA is a multi-purpose, high-density, reprogrammable logic gate array. Compared with traditional technologies, FPGA is not only convenient to design, flexible and fast to verify, but can also greatly reduce R&D time, design costs and design risks. At the same time, the system combining FPGA technology, microcontroller and radar display and control interface is applied to the design of high-performance radar signal processors, which can improve system integration, reduce circuit scale, and thus improve reliability. It can meet the requirements of modern radar signal processing systems in terms of speed, volume and design flexibility.

1 Working principle of the ground interrogation encoder of the air traffic control secondary radar

1.1 Encoder Function Description

The transceiver system of the ground station of the air traffic control secondary radar consists of three parts: encoder, interrogator and receiver. As shown in Figure 1, the encoder is the center of the entire radar and has three functions:

(1) Generate the synchronization pulse of the whole machine. It can work in two modes: external synchronization and internal synchronization. When the synchronization pulse works in internal synchronization, that is, when the secondary radar works independently, it generates a whole machine synchronization signal S0 with a repetition frequency of f=150~450 Hz. When the secondary radar and the primary radar work together, the primary radar provides the whole machine synchronization trigger signal, that is, when external synchronization is used, the repetition frequency f2 of the secondary radar and the repetition frequency f1 of the primary radar have the following relationship:

①When 150 Hz≤f2≤450 Hz, f2=f1;

②When 450 Hz

③When 900 Hz

Civil aviation regulations stipulate that f2≤450 Hz. The choice of repetition frequency depends on the size of the effective distance.

(2) Generate various inquiry modes.

The transmitter generates a 1 030 MHz RF pulse under the modulation of the interrogation pulse and sends it to the antenna through a three-terminal circulator. Under the control of the synchronization pulse, the antenna enters P1 and P3 into the sum channel and P2 into the difference channel. The receiver converts the 1 090 MHz RF response signal into a video signal and sends it to the terminal device for processing.

1.2 Encoder synchronization signal S0 generation principle

Where: Rlmax is the maximum interrogation distance; λI is the interrogation RF wavelength; GI is the interrogation antenna gain; GR is the response antenna gain; Prmin is the transponder receiver sensitivity; Pr is the transmission power of the ground transmitter; LI is the three-terminal circulator and feeder system loss; LR is the transponder feeder gain.

The interrogation period corresponds to the S0 synchronization signal period. Combined with the parameters of the actual project, the above formula is used to calculate the ratio of the interrogation time of 1 μs to the interrogation distance of 150 m. When the effective range of the secondary radar monitored by the manual route is 450 km, the corresponding interrogation period is 3.5 ms; when it is about 370 km, the corresponding interrogation period is 2.5 ms. When the effective range for airport terminal area III monitoring is 140 km, the corresponding interrogation period is 0.000 9 ms. [page]

1.3 Encoder system structure

Figure 2 shows the signal processing block diagram of the encoder. It uses a signal processing system that combines a radar display and control interface, a microprocessor, and an FPGA chip. The design of the encoder mainly implements the above three functions (see Section 1.1). The IPcore technology is used to extract the interface downlink data acquisition and microprocessor commands, and the frequency division circuit is used to generate the clock required by each module. The synchronous coding signal S0 is generated according to the query command. This encoding generates the regular mode and its alternating mode, and the S-mode query signal. A digital oscilloscope can be used for real-time measurement; the RF component can test the coded signal and generate a linear detection signal. After A/D conversion, it is sent to the IPcore to collect the digital signal and uploaded to the interface to qualitatively display the waveform.

2 Encoder interrogation signal format

2.1 Normal mode

According to the regulations of ICAO, there are six conventional interrogation modes, namely 1, 2, 3/A, B, C, and D modes. The time relationship between P1 and P2, and P1 and P3 in various modes is shown in Table 1.

Among them, modes 1 and 2 are dedicated to military identification interrogation; mode 3/A is used for military and civilian identification interrogation; mode C is used for high-altitude interrogation; mode D is used as a backup interrogation mode, and its interrogation content is still under discussion. These interrogation modes are composed of pulse pairs with different intervals, and their time relationship is shown in Table 1. Among them, the first pulse is called P1; the second pulse is called P2; and the third pulse is called P3. The format of pulses P1, P2, and P3 is a pulse width of (0.8±0.1)μs, the rising edge is between 1 and 5 μs, and the delay is between 0.2 and 5μs. Pulses P1 and P3 are both transmitted through the interrogation channel, and different time intervals are allowed between them.

2.2 Mode S interrogation signal format

Figure 3 shows the S-mode interrogation format. The first two pulses P1 and P2 have a pulse width of 0.8 μs and an interval of 2.0 μs. After the P2 pulse is a long pulse P6, whose duration is its pulse width, which is 16.25 μs or 30.25 μs, and there are many phase-inverted pulses, which are used to carry the transmitted data. The last 24 bits of P6 are the aircraft address, which is obtained through a full call interrogation. Among them, the first inversion is located 1.25 μs after the leading edge of the pulse, that is, P5 is a "synchronous phase inversion" signal, which is provided to the S-mode transponder as always synchronization, so as to decode the subsequent data accordingly; the synchronous phase inversion pulse is also used as a clock reference for the transmission of the reply signal. The interrogator measures the distance of the aircraft by calculating the time interval between the transmission of the synchronous phase inversion pulse and the first received reply pulse. The data is transmitted through a DPSK signal with an interval of 0.25 μs for the inversion position, resulting in a data bit rate of 4 MHz. Depending on the requirements, the bits of the entire transmitted data are 56 bits or 112 bits.

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2.3 S-mode parity and address

The last parity 24b information of the S-mode P6 data bits is calculated by improved cyclic redundancy (CRC) coding, and its polynomial is as follows:

Parity is calculated at the transmitter and added to the message along with the 24-bit aircraft address. At the receiver, parity is calculated again and compared to the parity and address information in the signal to determine if the message was sent correctly. The polynomial G(x) helps with error detection and correction and can be implemented using a shift register, the circuit of which is shown in Figure 4. The first 32 bits (or 88 bits for the long S mode) are sent unmodified, but are multiplied by G(x) at the feedback end of the shift register as they are sent. For the last loop the feedback end of the detected message is disconnected and replaced by the 24-bit address bits. The result is that the last 24 bits of the message contain the 24-bit parity field, added to the aircraft address and multiplied by G(x).

3 Encoder Design Process

The FPGA design flow chart of the encoder is shown in Figure 5. First, the control command of the radar control interface is extracted to determine the interrogation mode and interrogation method (interrogation alternating method). Combining the S0 generation principle and radar interrogation distance theory, the S0 synchronization signal is generated using counting frequency division coding.

If it is the normal mode, under the trigger of the S0 synchronization signal edge, according to the different control commands of the software control interface, the six single-mode (see Table 1) interrogation signals of the periodicity are encoded and generated respectively; and the corresponding periodic extraction signals are generated, and the corresponding encoding signals are generated in combination with the alternating mode.

If it is an S-mode inquiry, the design process is: first generate the leading pulse P1, P2 and data bit synchronization signal P5 of the S-mode, then determine whether it is a short S-mode (P5 data bit 56 b) or a long S-mode (P6 data bit 112 b), then call the dual-port RAM IPcore module inside the XCV600E for data acquisition, and perform parity address check encoding on the last 24 b of the aircraft address data bit of the S-mode. The check rule is shown in Figure 4. Then perform DPSK modulation encoding on the check result, and then generate an S-mode inquiry signal according to the signal format of the S-mode under the control of the data synchronization bit signal P5 (see Figure 3). [page]

4 Simulation waveform of inquiry signal

4.1 Simulated waveform of the normal mode 1:1:1 alternating interrogation signal

First, the synchronous trigger signal S0 is generated, which is changed by manual operation on the radar display and control interface, and has different periods corresponding to different monitoring ranges of the secondary radar. Generally, the period of S0 is 2.5 ms, 3.5 ms, and 0.0009 ms.

When the period of S0 is 3.5 ms, the simulation result is shown in Figure 6. The FPGA clock of XCV600E is 40 MHz, which generates a periodic S0 signal. The clock required by each module is generated by counting 4 times, 8 times, and 10 times. If the period of S0 is changed, it can be generated in a similar way; the second is the generation of the three-three alternating interrogation mode. As shown in Figure 6, in the interrogation control interface, any 3 of the 6 normal modes are selected. Triggered by the rising edge of the synchronous coding signal S0, the interrogation mode mode_1 is generated in the first S0 period, the interrogation mode mode_2 is generated in the second S0 period, the interrogation mode mode_3 A is generated in the third S0 period, and the interrogation mode mode_1 is generated in the fourth S0 period. The periodic generation according to this rule is the three-three alternating interrogation mode. Among them, S1_revert, S2_revert, and S3_revert are periodic extraction signals generated by the cyclic state machine, which periodically extract the coding signals of mode 1, mode 2, and mode 3 A respectively. The coding generation methods of other single modes are similar.

4.2 S-mode CRC checksum encoding and decoding simulation waveform

According to the polynomial circuit rule of the P5 bit parity address check of the S-mode interrogator encoder (see Figure 4), Matlab software is used to establish a shift register composed of 24 D flip-flops for simulation. As shown in Figure 7, the simulation results take P5 as 56 b as an example, data is the original P6 data signal, and data is the sequence of "1111111111011010100110101001000000110111111101001100001000". Among them, the last 24 bits represent the aircraft address (the aircraft address is first obtained by "all-call inquiry" and the verification is "roll-call inquiry"); encode is the verification output, and its sequence is "11111111101101010011010100100000000101101010000100110000"; then encode is used as input and decoded according to the transponder decoding circuit, and the decoding result is decode. It is found that the decoding result is the same as the original input data, which ensures the correctness of the verification code design.

5 Conclusion

The high-performance secondary radar ground interrogation encoder is designed by using the high-speed computing power of FPGA and IPcore technology. It is not only adaptive and controllable in data acquisition and signal encoding, but also solves the real-time problem of radar signals, completes the single-chip FP-GA integration of multiple complex signal processing, and effectively solves the contradiction between small circuit board size and large storage space, thereby improving the integration of the system and further saving resources. At the same time, the architecture technology combined with "software display and control interface + FPGA + MCU" makes it easier to become a micro system.