Design of communication system baseband verification platform based on FPGA

1 Introduction

In the field of communications, especially wireless communications, with the continuous updating of technology and the release of new standards, designers need a high-speed general-purpose hardware platform to implement and verify their communication systems and related algorithms. As a large-scale programmable logic device, FPGA (field programmable gate array) has flexible architecture and logic units, high integration, wide application range, short design and development cycle, low design and manufacturing cost, advanced development tools and real-time online inspection, and is widely used in product prototype design and product production.

Compared with traditional DSP (digital signal processor) or GPP (general-purpose processor), FPGA shows very strong performance in certain signal processing tasks. It has the advantages of high throughput, flexible architecture and algorithm, parallel computing, allocated storage and dynamic configuration. Therefore, it is very suitable for designing and verifying the baseband processing part of high-speed communication systems.

This paper proposes a communication system baseband design verification platform based on Xilinx Virtex-Ⅱ series 3 million gate FPGA devices. It is suitable for the prototype design of high-speed communication system baseband and the implementation of related algorithms, and has been successfully applied to the design of OFDM baseband system based on IEEE 802.1la.

2 System platform composition and functions

The communication system baseband design verification platform mainly consists of the following components: power supply, FPGA and peripheral circuits, clock and reset circuits, and analog-to-digital and digital-to-analog conversion circuits. The overall block diagram of the platform is shown in Figure 1.

The functions of each unit module are as follows:

• Power supply part: responsible for supplying power to FPGA and other circuits.
• FPGA and peripheral circuits: mainly composed of two 3 million gate FPGA devices. The configuration circuit is used to complete the automatic configuration of the FPGA after startup. Other major peripheral circuits include memory (SRAM and SDRAM) and serial communication circuits.
• Clock and reset circuit: Provides system clock and reset signals for FPGA.
• Analog-to-digital and digital-to-analog conversion circuits: mainly an ADC for converting digital signals into analog signals , and a DAC for converting analog signals into digital signals .

The working principle of the whole system platform is as follows: two FPGAs are designed as a transmitter (FPGA_TX in Figure 1) and a receiver (FPGA_RX in Figure 1). After the test vector enters the transmitter, it is baseband encoded and modulated and converted into a baseband analog signal through the DAC. The ADC and receiving circuit receive the signal transmitted by the cable, convert it into a digital signal, and restore it to the original data after demodulation and decoding by the receiver, and compare it with the test vector to obtain performance indicators such as bit error rate.

3 Circuit Implementation of Functional Units

3.1 FPGA and its configuration circuit

VirtexⅡ series FPGA is the first platform-level FPGA device for high-performance programmable solutions launched by Xilinx. Virtex-Ⅱ series devices are designed with advanced 0.15 μm/0.12 μmCMOS 8-layer metal hybrid process, with a core voltage of 1.5 V. It can support multiple interface standards according to different input and output reference voltage designs, and the internal clock frequency can reach 420 MHz. It is considered to be an ideal design with high speed and low power consumption.

Virtex-Ⅱ series device features:

(1) The internal clock frequency can reach 420 MHz, and the input and output rates can reach up to 840 MHz.

(2) Built-in 18x18 dedicated hardware multiplication circuit and look-ahead carry logic chain to achieve high-performance arithmetic processing functions.

(3) High-performance internal memory Select RAM, each block memory capacity is 18 KB. It provides up to 3 MB of block storage resources and 1.5 MB of distributed memory resources.

(4) Up to 12 digital clock managers (DCMs) and 16 global clock multiplexing buffers provide a flexible system clock solution.

(5) Virtex-Ⅱ uses digital controlled impedance matching technology (DCI), which can reduce system instability caused by impedance matching problems and reduce the complexity of PCB caused by terminal matching resistance.

This platform uses two 3 million gate Virtex-Ⅱ FPGA devices, model XC2V3000C. Considering compatibility and scalability, the FFl152 package is selected. This package is compatible with the FPGA pins of XC2V4000/6000/8000, which is convenient for system upgrades.

The configuration information of Virtex-ⅡFPGA is stored in SRAM. After power failure, the configuration information is lost and needs to be reconfigured and downloaded after power on. Virtex-Ⅱ series devices have 5 configuration modes: JTAG/Botmdarv Scan, Master Scrial, Slave Serial, Master SelectMAP, and Slave SelectMAP. Among them, Master SelectMAP and MasterSerial require the use of Xilinx dedicated PROM. [page]

This design uses the JTAG/Boundary Scan configuration mode, which mainly completes all configuration tasks through four dedicated configuration signal lines. Two configuration methods are provided. One is online download configuration, which uses a download cable to connect the FPGA's JTAG port to the computer's parallel port and use software to complete online download. The other is to use the SystemACE solution. After power-on, the SystemACE controller reads the configuration file in the CF memory and configures the connected FPGA device through JTAG.

SystemACE CompactFlash (CF) uses memory based on the CFACompactFlash standard, which consists of a CompactFlash storage module and an ACE controller. The ACE controller has built-in control logic and can configure the target FPGA chain through any ACE controller interface (CompactFlash interface, CFGJTAG interface, TESTJTAG interface, and system microprocessor interface). The CompactFlash interface provides support for CompactFlash memory cards. The configuration data size required for a single Virtex-Ⅱ FPGA is 300 Kbit-29.O Mbit, which means that more than 250 Virtex-Ⅱ series FPGAs with the maximum capacity can be configured using a Svs-temACE CF solution. Designers can flexibly change the density of ACE Flash as needed.

The SystemACE configuration diagram is shown in Figure 2. After the FP-GA design is completed, the designed download configuration file is generated by the software, and the file is placed in the CF memory card through the CF card reader. When the platform is powered on, the ACE controller reads the configuration file in the CF card and downloads the data to each FPGA through the JTAG chain to complete the automatic configuration. You can also connect the TEST JTAG interface through the JTAG download cable to directly configure the FPGA online.

3.2 Clock Circuit and Reset and Voltage Monitoring Circuit

This platform uses two independent active crystal oscillators to provide 20 MHz clocks, which are used as the clock sources for the receiver and transmitter respectively. Since 20 MHz clocks are required in many places on the board (such as ADC and DAC ), relying solely on crystal oscillators to supply clocks may not only result in weak driving force, but also cause large clock offset or jitter. The clock driver IDT74FCT38074 is selected to provide the clock for the system. This is a 3.3 V powered, CMOS process 1-drive 4 clock driver with a maximum input clock of 166 MHz and 4 low-offset in-phase clocks. Through two IDT74FCT38074s, accurate clocks are provided for each module of the receiver and transmitter respectively. After the input clock enters the FPGA, it can be processed by the frequency division and multiplication of the DCM to provide the required clock for each functional module inside the FP-GA.

In the Virtex-Ⅱ device, all DCM modules are distributed to the device through clock multiplexer logic. The 16 global clock buffers provided can realize the control of 16 clock domains, ensuring that the clock output of the DCM module has the minimum transmission delay (skew).

The reset and voltage monitoring circuit uses MAX708SCPA, which provides power-on automatic reset and manual reset. The PFI pin of MAX708SCPA is the monitoring voltage input terminal. When the PFI input voltage is lower than 1.25 V, the PFO pin outputs a low level to indicate that the voltage is too low. In this design, it is used to monitor the FPGA 1.5 V core voltage. The switch button S8 provides manual reset. The circuit diagram is shown in Figure 3.

3.3 Digital-to-Analog and Analog-to-Digital Conversion Circuits

This platform is used to verify the communication baseband system. The I and Q signals output by the transmitter need to be converted into analog signals through a digital-to-analog converter (DAC) , and the receiver converts the received signals into digital signals through an analog-to-digital converter (ADC). The ADC and DAC used in this platform design are AD9238 and AD9765 from ADI.

AD9238 is a dual-channel 12-bit ADC. The speed grades are 20MS/s, 40MS/s and 65MS/s. The power consumption is 180mW~600mW, which is suitable for applications requiring low power consumption and small PCB area. The signal-to-noise ratio (SNR) of AD9238 is 70 dB, and the spurious-free dynamic range (SFDR) is 85 dBc. With an on-chip broadband differential sample-and-hold amplifier (SHA), the user can select a variety of input ranges and offset voltages, including single-ended input. AD9765 is a dual-port, high-speed, dual-channel, 12-bit CMOS digital-to-analog converter (DAC). It integrates 2 high-performance 12-bit TxDACs. The update rate can reach 125 MS/s, the spurious-free dynamic range (SFDR) is 75 dBc, and the gain offset matching rate is 0.1%. The output is a differential current with a full amplitude of 20mA. [page]

In this design, AD9238 works in 2Vp-p differential working mode, uses internal reference voltage, and two channels work in shared voltage reference mode. The input differential amplitude is 2 V. The signal clock input can use the 20MHz output of the clock driver or be provided by FPGA, and the maximum sampling rate is 40 MS/s. The two channels of AD9238 select AD8138 as the op amp driver to provide differential input signals for ADC. AD9765 works in dual-port mode, and the gain control of the two channels can be adjusted separately, using an internal 1.2 V reference voltage. The clock input can also use the 20 MHz output of the clock driver or be provided by FPGA. The connection diagrams of AD9238 and AD9765 with FPGA are shown in Figure 4 and Figure 5 respectively.

3.4 Power Circuit

The system requires two power supply voltages for normal operation: one is the core voltage of the FPGA device, 1.5 V; the other is the input and output interface voltage of the FPGA device, 3.3 V, which is also used to power other devices.

This design uses a low voltage, high current linear regulator (LDO) power supply solution suitable for FPGA applications . The power input uses a standard ATX power supply interface and can be powered by an ATX power supply. The +12 V input directly powers the fan for FPGA cooling. The +5 V input is converted to 3.3 V and 1.5 V voltage outputs by TPS75533 and TPS75415 of Tl Company respectively. TPS75533 is an LDO with a minimum voltage difference of 250 mV and can provide 3.3 V, 5 A output. TPS75415 can provide 1.5 V, 2 A output, and its fast transient response can effectively improve system performance. LDO adopts the linear regulation principle, with very small output ripple and simple peripheral circuit. It only requires external input and output capacitors to work. The disadvantages are low voltage conversion efficiency, high heat generation, and high requirements for heat dissipation control. The TPS75533 uses a TO-220 package, which can effectively dissipate heat through the heat sink on the back, while the TPS75415 uses a small TSSOP package of Power PADTM, which provides 2W heat dissipation power, improves heat dissipation and saves space. [page]

A protection circuit consisting of a Zener diode and a Schottky diode is added between the 3.3 V and 1.5 V voltages to ensure that the difference between the FPGA core voltage and the interface voltage is within a certain range to prevent device damage.

4 OFDM Baseband System Verification Platform Design

The FPGA-based communication system baseband design verification platform is very suitable for the baseband design of high-speed wireless communication systems. This platform can be used to verify the simplified prototype design of the OFDM baseband system based on IEEE 802.1la. The design block diagram is shown in Figure 6.

It has been verified that the platform can realize the sending and receiving functions of the OFDM prototype and can effectively verify the actual performance of the synchronization and channel estimation algorithms.

5 Conclusion

The FPGA-based communication system baseband design verification platform uses large-capacity, high-performance FPGA devices to provide an effective hardware implementation platform for the baseband design of the communication system. The combination of FPGA-based implementation and verification with computer simulation will greatly accelerate the rapid prototyping of the baseband part of the communication system, and greatly facilitate the verification of various algorithms with high requirements for real-time performance and computing power.