Research and implementation of pseudo code capture based on FPGA sliding correlation method

introduction

For the spread spectrum communication mode of code division multiple access, useful information can only be decoded when the local pseudo code at the receiving end is in the same phase state as the pseudo code at the transmitting end. Therefore, the capture and tracking of the spread spectrum sequence phase is the key to the spread spectrum communication system, and the capture of the pseudo code sequence phase is particularly important. The sliding correlation method is one of the commonly used methods. The spread spectrum communication system requires real-time performance and a high data processing speed, which is exactly the advantage of FPGA. Therefore, in the spread spectrum communication system, FPGA chips are widely used as pre-processing chips.

Implementation principle

Principle Analysis

The spread spectrum signal received by the receiver can be expressed as:

Among them, P_{r} is the received signal power, τ_{d} is the transmission delay, D(t) is the information code, PN(t) is the pseudo code, and n(t) is the additive noise of the transmission process. The task of the spread spectrum receiver is to remove the PN(T-τ_{d}) pseudo code term and the cos(ω_{0}t+φ) carrier term to obtain the information data DZ(t).

VCO outputs I and Q signals:

Through the in-phase orthogonal multiplier, we get:

Using the correlation characteristics of the PN code, that is, when the phase is aligned, the correlation result is the largest. When the carrier and code phases are aligned, the output after cumulative cleaning (low-pass filtering) is:

The influence of the carrier on the correlation result can be removed by adding the squares and obtaining the correlation peak.

Implementation block diagram

In the direct sequence spread spectrum system, the capture of pseudo code is an important structure of the code synchronization system and an indispensable part of the direct spread spectrum system. If the receiver wants to decode the signal spread by pseudo code, the receiver must be able to generate a pseudo code sequence that is the same as the sender (to ensure the maximum correlation value), and the local pseudo code rate and phase must be consistent with the received pseudo code. It is easy for the agreed receiver and sender to use the same pseudo code, but if the transmitted information is to be obtained from the despreading correlator, it is far from enough to simply ensure the same code type. Because even if the pseudo random code is the same, when the phase difference is greater than one chip, their correlation peaks will completely disappear. In actual communication, due to the instability of the clock of the receiver and transmitter, the uncertainty of the receiving and transmitting time, the channel transmission delay and interference and other factors, the phase difference between the receiving and transmitting pseudo code sequences is random. Therefore, the first step of despreading is to capture a phase state consistent with the local pseudo code in the pseudo code phase of the received signal. When this state occurs, the correlator will have a correlation peak output. If the peak value exceeds the threshold, it is determined that the phase has been captured, and the capture action is stopped immediately and the phase tracking state is switched; if it is less than the threshold, the local code phase is changed and the capture is continued. The system implementation principle is shown in Figure 1.

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Implementation

According to the phase capture method, it can be divided into: continuous phase sliding correlation method and discontinuous phase correlation method improved on this idea.

Continuous Phase Sliding Correlation Method

This method is to change the local pseudo code clock rate and maintain a suitable offset with the transmitting end pseudo code clock rate, so that the pseudo code phase in the received signal and the local pseudo code phase slide relative to each other in the correlator. The phase capture of this method is continuous, so the correlation peak is a continuous quantity. Once the correlation value exceeds the capture threshold, it indicates that the correct phase has been searched, and the receiver immediately restores the local pseudo code clock rate (both the receiver and the transmitter use a very stable oscillator source, so their code rates can be basically consistent), stops phase sliding, and starts the tracking circuit to further reduce the phase difference (which means that the correlation increases), obtain a higher despreading signal-to-noise ratio, and meet the subsequent demodulation threshold requirements. The capture time and detection probability of this capture method are contradictory. For example, for a PN code with N=215 bits, the maximum relative sliding rate between the two pseudo codes is about 5kc/ps, and the time required to traverse all its related states is 6.55S. In the actual communication process, when the pseudo code phase is lost due to interference and other reasons and needs to be recaptured, such a long capture time will seriously affect the communication quality, so it is not advisable. From the above analysis, we can see that this capture method has high phase search accuracy but also leads to a long capture time. It is rarely used in practice, but its idea is worth learning from. The discontinuous sliding correlation method is an improvement on this basis.

Discontinuous Phase Sliding Correlation Method

The difference between continuous and discontinuous is the amount of phase sliding change in the search. The latter method changes the continuous phase search into a jumping search, that is, the phase sliding amount between the two codes is no longer a continuous phase sliding with a certain step amount. The discontinuous sliding correlation method uses a phase search circuit to make the local pseudo code phase jump and change with a certain step value during the capture process, so that the time to traverse the entire pseudo code is greatly reduced. Compared with the former method, its receiving and transmitting pseudo code clock rates are consistent, so that there will be no inconsistency in the code chip width, resulting in a decrease in the correlation peak. The relative change of the local pseudo code and the received pseudo code phase is achieved by the search circuit's advance and lag control of the pseudo code generator clock, so the phase search circuit (as shown in Figure 2) is the key to the former. The following focuses on the implementation method of half-code chip sliding.

Capture method 1 (slide step is TC/2)

Clock inversion method:

As shown in Figure 1, when the square of the signal envelope is less than the threshold, the control signal is output, and the CLK in Figure 2 is inverted. The inverted result is equivalent to triggering with the falling edge of the original CLK clock. After being divided by two, it is used as the clock of the pseudo code generator. At the same time, CLK is used as the clock of the shift register. The output of the three-bit shift register is equivalent to shifting half a chip. The FPGA simulation result is shown in Figure 3.

In the figure, data1, data2, and data3 are the outputs of the three-bit shift register, 01 represents +1, 11 represents 1, clk1 is the output of the code NCO, and clk2 is its frequency division by two. This method requires multiple inversion operations on the clock in the entire system, which will bring serious timing problems and make the system working timing unsatisfactory. In order to solve this problem, an improved method can be used.

Capture method 2 (slide step is TC/2)

Improvements to the clock inversion method:

This method uses a trigger structure, takes 2 times CLK as input, and CLK as the enable terminal. The FPGA's own IP core-phase-locked loop is used to advance the CLK phase and wrap the rising edge of 2 times CLK. The output of the trigger is CLK. The FPGA simulation result is shown in Figure 4. In the figure, co is the input terminal, and pn is the output of the phase-locked loop as the enable terminal. The enable terminal is inverted, and the movement of half a code chip can be completed through the circuit structure of Figure 2. However, if half of the CLK is phase-locked at the same time, if multiple channels are realized, since there are only two phase-locked loops inside the FPGA, the practicality is limited.

Capture method 3 (sliding step is TC/2)

Pulse shift method:

This method uses an XOR gate, as shown in Figure 5, to make the output CLK of the code NCO XOR with a signal. This signal is usually at a high (or low) level. Once it receives a value lower than the threshold, it outputs a low (or high) pulse. After XORing with CLK, it is equivalent to adding a pulse to the original CLK clock. After passing through the circuit shown in the figure, the pseudo-code generator advances half a phase. After passing through the shift register, it can realize the movement of half the code phase (advancing half a code chip).

The FPGA simulation result is shown in Figure 6. In the figure, CLK1 is the output of the code NCO, CLK2 is its frequency divided by two as the clock of the pseudo code generator, pn1 is the output of the pseudo code generator, and k1 is a signal. It usually outputs a high level. When the threshold detection result is low, it outputs a low pulse and CLK1 XOR output, and the result is CLK3. It can be seen from the simulation diagram that CLK3 has an additional pulse relative to CLK2 when k1 is a low pulse.

Download to FPGA, use SIGNALTAP, the test results are shown in Figure 7. In the figure, CLK1 is the code NCO output clock, CLK2 is the output of the XOR gate. It can be seen from the figure that when the threshold detection is low, CLK2 has one more pulse than CLK1. The test results are consistent with the simulation results. [page]

Achieve Results

Through the above analysis, combined with the relevant theories of spread spectrum communication, we can know that to achieve signal capture, we must conduct a two-dimensional search of the carrier and pseudo code phase. First, the received signal is digitally down-converted to zero intermediate frequency I and Q signals, and then despread with the local PN code. The result is compared with the threshold value. If it is less than the threshold, the half code chip is sequentially moved according to the previous analysis method until the square of the envelope is greater than the threshold and enters the tracking state. The capture circuit is shown in Figure 1.

Using the above method, a certain spread spectrum signal is captured in practice.

Signal parameters

• Intermediate frequency 40MHz;
• The modulation style is DS-BPSK;
• The pseudo code length is 1024;
• Data rate 5Kb/s;
• Sampling clock 60MHz;

Functional description of each module

Digital Down Conversion:

The output of the carrier NCO and the input signal are digitally down-converted in the multiplier, the function of which is to remove the input signal carrier frequency while retaining the code for baseband correlation.

Digital Correlator:

The function of the accumulator cleaner is to integrate and accumulate the results of multiplying the I and Q signals after digital orthogonal down-conversion with the local regenerated pseudo code. An accumulator is used to accumulate each bit of the multiplication of the input signal after digital mixing and the local code. After a certain period of integration (12,000 times in this solution), a correlation value of a data bit is obtained. This correlation value is compared with the preset threshold to make a capture decision. If it is less than the threshold, it is considered that the capture has failed, the accumulation result is cleared, and after sliding half a code chip, the accumulation integration is performed again. The accumulator cleaner accumulates data for one code cycle and outputs a relevant accumulation value. The maximum capture time is 0.4094 seconds (0.2mS*2047).

Carrier NCO:

The carrier NCO is an important component of the carrier tracking loop. Its main function is to generate a local replica carrier signal. The carrier NCO module is equipped with a frequency control word input interface. The module accumulates the input control word through a 32-bit phase accumulation to obtain the mapping address of the phase value, and obtains the sine and cosine signals through a table lookup. The carrier loop keeps tracking the carrier frequency and phase of the received signal by continuously adjusting the frequency word of the carrier NCO.

Code NCO:

The code NCO is the core of the code tracking loop. Its main function is to provide an accurate clock signal for the regenerated pseudo code generator to ensure the code capture and tracking of the received signal. The code NCO is set with a frequency control word, which is responsible for the code rate adjustment and code phase delay.

Achieve Results

A/D uses AD9288-100, which is an 8-bit conversion result. The highest operating frequency can reach 100M. The digital down-conversion and capture circuit is implemented in EP1C12Q240C8 (Cyclong). The intermediate test results of the operation are shown in Figure 8. In the figure, pn2_clk is the NCO output clock, x_pn is the pseudo code, c1_data and s1_data are the I and Q carrier signals generated by the carrier NCO for down-conversion. pn_e, pn_p, and pn_l are the advance, immediate, and lagging codes output by the shift register, respectively, and they differ by half a chip.

The final capture result is shown in Figure 9. In the figure, ad_data is the received digital intermediate frequency signal, and last_data is the final capture result.

Save the data, and the relevant results in Matlab are shown in Figure 10.

Conclusion

The pulse adding method can make the local code phase advance by half a chip phase, realizing discontinuous phase sliding correlation. The circuit structure is simple and easy to implement in FPGA. It is a simple and practical method that has been adopted in actual system design and achieved ideal results.