Design of railway crossing image monitoring system using DSP

At present, there are basically three types of railway crossings: manned, manned and unmanned. For a long time, the railway department has invested a lot of manpower and material resources in manned and manned crossings, and has taken safety measures. In particular, the technical equipment of manned crossings with automatic alarm signals as the main facilities has been basically perfected, creating better conditions for the safety management of the crossings themselves. However, the automatic alarm device of the crossing only considers the problem of strengthening the supervision of the crossing itself and preventing accidents at the crossing, but does not take into account the problem of how to prevent crossing conflicts in time when abnormal situations occur when moving trains are at the crossing. In order to further control the safety of the crossing, a set of railway crossing image monitoring system based on DSP is designed, so that the driver can receive the final result of the system's judgment on the crossing in time through GSM-R within an appropriate distance before the train passes through the crossing. This is of great significance to ensure the safety of trains and vehicles and pedestrians passing through the crossing.

System overall framework

Basic system components

As shown in Figure 1, the system is mainly composed of industrial cameras, data buffers, DSP processors, CPLD chips, crossing sending equipment and locomotive receiving equipment. Two industrial cameras are installed at both ends of the crossing to record the operation of pedestrians and vehicles at both ends of the crossing. The data buffer is used to temporarily cache the image data collected by the camera after conversion by the USB interface circuit, in preparation for the image processing part to call. The CPLD chip and DSP processor are the core of the entire hardware system, which are mainly responsible for real-time processing and analysis of the data of the railway crossing, so as to determine whether the crossing has a fault. The mobile hard disk is used to store photos when the crossing fails.

How the system works

The working principle of the system is as follows: when the train approaches the crossing at 1500m to 2000m, the cameras installed on both sides of the crossing start to shoot the situation around the crossing in real time, and the collected video images are sampled by A/D to obtain dynamic sequence image frames, and the image frames are sent to the data buffer area. Under the control of CPLD, the data in the data buffer area is read into DSP. According to the algorithm designed by the system, the crossing image data is processed to determine whether there is a fault at the crossing. If there is a fault at the crossing, the relevant images are stored in the mobile hard disk; at the same time, the result code of the system analysis is transmitted to the specific receiving device of the train locomotive through the railway wireless communication system GSM-R. The locomotive driver knows the situation of the crossing ahead according to the received signal code and takes corresponding emergency measures to avoid the occurrence of crossing accidents.

System design solutions

Introduction to the core components of the system

TMS320C6202 is produced by TI in the United States. It is a fixed-point digital processor with a main frequency of up to 250MHz and a maximum processing capacity of 2000MIPS. It has an eight-stage pipeline and can execute 8 32-bit instructions per instruction cycle. It has a very long instruction word structure and supports 32-bit, 16-bit, and 8-bit data. It has four main DMA channels and one DMA auxiliary channel. Through the 32-bit EMIF interface, it allows external connection to different devices, including SBSRAM, SDRAM, ASRAM, FLASH, and FIFO. EPM7128SQC100 has a logic array block (LAB), macro cells, extended product terms (shared and parallel), programmable wiring array (PIA) and I/O control block. It provides a low-power working mode that allows the user-defined signal path or the entire device to work in a low-power state. It contains a programmable security bit to control the readout of the internal configuration data of the device. This chip can be reprogrammed quickly and effectively, and it is guaranteed to be programmable and erased more than 100 times. FN74V245 is a synchronous high-speed buffer device produced by TI in the United States. It has the characteristics of high speed, low power consumption CMOS and clock-driven synchronization. As a synchronous device, it means that each end of the FIFO (read/write) uses an independent clock drive signal. The clock signals at both ends can be asynchronous or cooperative, which can make the two ends of the FIFO device run at two different speeds and complete the speed matching of two different frequency devices. Y7C 1339-166AC is produced by Cypress Semiconductor Company in the United States as DSP expansion RAM. The data transmission frequency can be up to 166MHz and the storage space is 128k×32.

System hardware design

The image data volume is large and the algorithm is highly complex. A design scheme for a railway crossing image monitoring system based on DSP is proposed. At the same time, the strong flexibility of field programmable gate array (FPGA) or complex programmable logic device (CPLD) is used to complete the timing logic control of the system. According to the signal flow, the hardware design of the system can be roughly divided into six modules: image capture, timing control, DSP image processing and image external storage, sending signal code and locomotive receiving signal code. The hardware structure of the system is shown in Figure 2, where the DSP uses TMS320C6202, the CPLD uses EPM7512BQC208-5, and the data transmission module uses Siemens' MC55 chip. Considering that the industrial cameras currently produced at home and abroad can directly output digital images and have USB interfaces, they are directly connected to FIFO through the USB interface circuit. The system uses CY7C1339B as the system's data memory to store digital video signals, and uses SS39VF400A as the system's program memory; the DSP is connected to these two memories through the DSP's external interface EMIF. As a high-speed cache, SN74V245 can effectively solve the huge difference between the speed of video acquisition and the speed of DSP processing. Its front end is connected to the USB interface of the camera, and the collected video data is written into the cache under the drive of the synchronous clock; its back end is connected to the 32-bit XBUS of the main processor DSP. The PEPM7512BQC208-5 chip is responsible for the coordination between DSPs, the control of complex peripherals and some communication work. The external interface is connected to SN74V245, TMS320C6202, SS39VF400A and mobile hard disk respectively.

System software design

The modular software design is adopted to divide the software into several relatively independent functional modules, and appropriate entry and exit parameters are arranged for each module, so that the modules can be connected to each other and combined flexibly and conveniently. The software of this system mainly consists of four parts: image acquisition module, image processing module, data transmission module and locomotive receiving module. This system is a real-time image processing system based on DSP. The main program of DSP runs through the operation of the entire system, including the movement and processing of the acquired image, the interface with the external memory SDRAM and Flash, the mobile hard disk and the crossing sending device, etc. For the convenience of program implementation, the main framework is implemented in C. In the specific algorithm implementation, some key codes are implemented by embedded assembly, and corresponding software optimization is performed to improve the program operation efficiency. After C6202 completes power-on startup or reset, the DSP program is loaded and started, the system initialization and the setting of various parameters are completed, that is, the system bootstraps, and then starts to wait for external interrupts. When the external interrupt NT 1 of the image acquisition is triggered, the DSP starts the internal acquisition chip of the camera, and the image acquisition module starts to run. When the FIFO is half full, the NT 3 interrupt is generated, and the DSP starts to move the image data through the written interrupt service subroutine. After collecting an image, an interrupt NT 2 is generated. Through the interrupt service subroutine, the DSP starts image processing. After the image processing is completed, the processing result needs to be sent to the gate sending device interface through the McBSP interface, and the crossing fault image is also sent to the mobile hard disk through the EDMA interface. Due to space limitations, this article only gives the main program flow chart of the DSP, as shown in Figure 3.

Conclusion

The DSP-based railway crossing image monitoring system is the result of the combination of digital image processing technology and wireless network communication technology. It truly realizes the automation and informatization of railway crossing safety management. The system design abandons the camera-monitor model of the traditional image monitoring system, and uses hardware chips (such as DSP, CPLD) and other devices to complete the computer's processing and control of digital images. The final result of the system is not to display the video image, but to identify and classify the targets in the video image; to determine whether there is a fault at the railway crossing,

The judgment result is transmitted to the train approaching the crossing in the form of code through the GSM-R network. The system can timely feedback the crossing information to the moving train, effectively solve the potential accident hazards at the crossing and provide guarantee for the safety of railway crossing.