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HPM6750 evaluation of Pioneer Semiconductor Step 2 (LVGL test) [Copy link]

 This post was last edited by arilink on 2022-5-14 17:04

LVGL stands for Light and Versatile Graphics Library. It is a free, open-source GUI library with exquisite interface, low resource consumption, high portability, responsive layout and other features. LVGL is developed in pure C language to achieve maximum compatibility (compatible with C++). It comes with nearly 30 kinds of small tools for developers to use, making it convenient for developers to build high-quality HMI interfaces. I personally think that LVGL's basic controls and overall effects are the first echelon of embedded GUI, comparable to TouchGFX.

The HPM6750 chip has 2 MB on-chip SRAM and the HPM6750EVKMINI development board has an external 16-bit SRAM capacity of 256Mb for use in complex projects.

This experiment uses a 7' 800*480 resolution screen connected to the HPM6750EVKMINI development board through the RGB interface.

Generate lv_demo_benchmark project and run the test. FPS is around 20

Generate the lv_demo_widgets project and run the test. The operation is relatively smooth. The test load is relatively large and the temperature of the chip has also risen.

It should be noted that the lv_demo_widgets example occupies a lot of resources, so you need to increase the allocated memory appropriately to display it normally, otherwise it will display abnormally.

Refer to the sample project, copy the demo code and modify the CMakeList file to generate your own lvgl project and build your own LVGL display code in the project. This part is relatively simple and has been tested on the PC. The program copied here has the same effect. The project mainly simulates an IOS volume adjustment and adds event callbacks to display the volume percentage through a Label.

Ok, let’s stop here for the LVGL test and continue to study the follow-up content...

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70MHZ? With such a high frequency, the screen pixels should be above 800X480, so the read bandwidth of SDRAM is almost fully utilized.   Details Published on 2022-5-16 12:42
 
 

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800M main frequency, how come the FPS is only 20, is it false? This is really incomprehensible, you can use the internal RAM as a buffer and the external RAM as a buffer to test and compare.

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The LVG in the official example uses 16-bit SDRAM as buffer. If SRAM is used, it is estimated to be 30fps. The SPI display tested runs LVGL, 240*280, which is 25fps+.  Details Published on 2022-5-15 16:07
 
 
 

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ilovefengshulin published on 2022-5-15 09:44 800M main frequency, why is the FPS only 20, is it false? This is really incomprehensible. You can use the internal RAM as a buffer and the external RAM as a buffer to measure...

The LVG in the official example uses 16-bit SDRAM as buffer. If it is replaced with SRAM, it is estimated to be 30fps. The SPI display tested runs LVGL, 240*280, which is 25fps+.

This post is from Domestic Chip Exchange

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Should the external sdram clock be 166MHz? If so, using a 16-bit data bus, the read bandwidth should be around 166*2/2=166MB/S, and the write bandwidth should be around 332MB/S. Using an 800X480 resolution screen, RGB565, 30MHZ pixel clock, 60 frames per second, the bandwidth of the RGB interface controller should be  Details Published on 2022-5-16 09:04
 
 
 

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RCSN posted on 2022-5-15 16:07 The LVG in the official example uses 16-bit SDRAM as buffer. If SRAM is replaced, it is estimated to be 30fps. The SPI display tested runs LVGL, 240*280, which is only 25 ...

Should the clock of the external SDRAM be 166MHz? If so, using a 16-bit data bus, the read bandwidth should be around 166*2/2=166MB/S, and the write bandwidth should be around 332MB/S. Using an 800X480 resolution screen, RGB565, 30MHZ pixel clock, and 60 frames per second, the bandwidth of the RGB interface controller is only 60MB/S, less than half of the SDRAM read bandwidth. This is a theoretical calculation, but in reality, we still need to dig deeper to find the reason for the low frame rate.

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SDRAM is 166, which is obtained by dividing a clock source of PLL2 by 333M. The read and write bandwidth of SDRAM is so much, but the clock of LCDC that drives the display is more than 70MHZ. Is the read bandwidth of the display similar to that of SDRAM? ? ? I have not tested it myself  Details Published on 2022-5-16 10:27
 
 
 

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ilovefengshulin posted on 2022-5-16 09:04 Should the clock of the external sdram be 166MHz? If so, using a 16-bit data bus, the read bandwidth should be around 166*2/2=166MB/S, ...

SDRAM is 166, which is obtained by dividing a clock source of PLL2 333M. The read and write bandwidth of SDRAM is so much, but the clock of LCDC that drives the display is more than 70MHZ. The read bandwidth of the display is similar to the read bandwidth of SDRAM? ? ?

I didn't bring this monitor with me when I was doing the review. 30FPS is the official number. I still need to study the details.

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70MHZ? With such a high frequency, the screen pixels should be above 800X480, so the read bandwidth of SDRAM is almost fully utilized.

This post is from Domestic Chip Exchange
 
 
 

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