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Published on 2022-5-14 17:02
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70MHZ? With such a high frequency, the screen pixels should be above 800X480, so the read bandwidth of SDRAM is almost fully utilized.
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Published on 2022-5-16 12:42
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ilovefengshulin
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Published on 2022-5-15 09:44
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Should the external sdram clock be 166MHz? If so, using a 16-bit data bus, the read bandwidth should be around 166*2/2=166MB/S, and the write bandwidth should be around 332MB/S. Using an 800X480 resolution screen, RGB565, 30MHZ pixel clock, 60 frames per second, the bandwidth of the RGB interface controller should be
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Published on 2022-5-16 09:04
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ilovefengshulin
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Published on 2022-5-16 09:04
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SDRAM is 166, which is obtained by dividing a clock source of PLL2 by 333M. The read and write bandwidth of SDRAM is so much, but the clock of LCDC that drives the display is more than 70MHZ. Is the read bandwidth of the display similar to that of SDRAM? ? ? I have not tested it myself
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Published on 2022-5-16 10:27
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Published on 2022-5-16 10:27
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