Research on A-ultrasound digital flaw detection system based on FPGA

Ultrasonic wave is a mechanical wave. Mechanical vibration and fluctuation are the physical basis of ultrasonic flaw detection. Ultrasonic wave propagates in the medium, and has the characteristics of wave superposition, reflection, refraction, transmission, diffraction, scattering, absorption and attenuation, and generally follows the principles of geometric optics. A-ultrasonic flaw detector uses amplitude modulation (Amplitude Modulation) display. On the display screen, the horizontal axis represents the depth of the object being tested, and the vertical axis represents the amplitude of the playback pulse.

There are many methods of ultrasonic flaw detection, which can be classified into pulse reflection method, penetration method and resonance method according to their principles. This system adopts pulse reflection method. Pulse reflection method is a method that uses an ultrasonic probe to transmit pulses into the test block to detect defects of the test piece according to the reflected wave. The pulse reflection method also includes defect echo method, bottom wave height method and multiple bottom wave method, etc. Here we only introduce the defect echo method. Figure 1 is a schematic diagram of the defect echo method. When the test piece is intact, the ultrasonic wave can be smoothly transmitted to the bottom surface, and there are only two signals in the flaw detection diagram, namely the surface emission pulse T and the bottom echo B, as shown in Figure 1 (a); if there is a defect in the test piece, there is an echo F indicating the defect before the bottom echo in the flaw detection diagram, as shown in Figure 1 (b).

The hardware principle structure of the whole system is shown in Figure 2, which mainly includes two parts: analog and digital. They are introduced below.

1 Analog part

The analog part of the system is mainly composed of transmitting circuit, limiting mechanism, high-frequency amplification, bandpass filtering, detection and other parts.

The transmitting circuit is mainly used to generate a high-voltage narrow pulse signal (400V) to stimulate the ultrasonic probe to transmit ultrasonic waves. Since the resonant frequencies of different probes are different, the width of the pulse excitation signal is required to be adjustable. In the design of the transmitting circuit, the FPGA provides the transmitting circuit with a low-voltage adjustable pulse width excitation signal, which is then converted by the transmitting circuit into a high-voltage narrow pulse excitation signal with a variable pulse width.

The amplitude limiting mechanism is to limit the voltage amplitude of some excessively large echo electrical signals, so as to prevent the excessive voltage from affecting the normal operation of the subsequent high-frequency amplifier and even burning the circuit components. The amplitude limiting circuit has a limit amplitude of about ±3V.

The high-frequency amplifier circuit is used to amplify the echo electrical signal, and the amplification range can be from -10dB to 110dB. Since the thickness of the test object steel plate is different, the strength of the echo signal is also uncertain. Therefore, the high-frequency amplifier circuit should be designed as a programmable amplifier circuit that can dynamically control the gain value, which can be achieved through the MCU.

The bandpass filter circuit controls the noise introduced during the signal amplification process. Since the transmission frequency range of the ultrasonic probe is relatively wide (400kHz～10MHz), if the amplifier passband range is fixed to 400kHz～10MHz, the filtering effect will inevitably be affected. In this paper, two sets of programmable bandpass filter circuits are designed, and their bandwidth ranges are 400kHz～2.5MHz and 2.5MHz～10MHz respectively.

There are usually two ways to display echo waveforms in ultrasonic flaw detection systems: RF display (non-detection display) and video display (detection display), as shown in Figure 3. RF display can maintain the waveform state, which is helpful for identifying the nature of defects; while video display is conducive to peak acquisition in order to determine the defect equivalent. In order to meet the requirements of these two displays respectively, a detection and non-detection switching circuit is added to the design, and the switching of the circuit is controlled by the MCU.

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2 Digital part

2.1 Microcontroller unit

The digital part of the system uses the microcontroller unit (MCU) as the control core of the entire ultrasonic detection system. Intel's 16-bit single-chip microcomputer MCS196kc is selected here. This MCU not only has 16-bit data calculation function, but also provides powerful control capabilities. In fact, the existing functions are mainly: (1) control the display module and keyboard interface module to realize the interaction of the human-computer interface; (2) complete the storage and printing of the test results; (3) provide reliable data transmission between the microcomputer; (4) realize the management of the power module; (5) adjust the amplification gain multiple of the operational amplifier in the analog part.

2.2 Real-time digital signal processing unit based on FPGA

FPGA is the core component of digital signal processing in the entire detection system. With its user-programmable characteristics and high internal clock frequency, a data processing chip dedicated to ultrasonic testing is designed, as shown in Figure 4. The chip is mainly composed of the following functional modules: (1) parameter register stack required for data processing; (2) narrow pulse generation module; (3) sampling delay control module; (4) data acquisition, storage, and compression module; (5) wave gate, DAC defect automatic judgment module; (6) wave gate defect automatic judgment module. Now, the signal processing process shown in Figure 4 is briefly described in conjunction with Figure 5: MCU continuously transmits square wave pulse signals to FPGA at a certain frequency, and each pulse signal will trigger a detection process. The rising edge of the pulse signal causes the narrow pulse generation circuit to start working and generate a narrow pulse excitation signal. After the excitation signal is generated, since the ultrasonic wave needs a delay time to pass through the coupling agent to reach the detection workpiece, after the narrow pulse signal is generated, the delay circuit will work to control the time when sampling starts. After a delay of (t2-t1), the ultrasonic wave reaches the surface of the workpiece and sampling begins. The processing unit first selects the corresponding data processing module according to the detected steel plate thickness. If the steel plate is a thin plate, the data acquisition and storage module will work; if the steel plate is a medium-thick plate, the data acquisition, compression, and storage module will run. After the sampling process is completed, within the time period (t4-t3), the processing unit automatically determines the defects of the echo signal in this sampling. If defects or missing waves are found, the flaw detection system will give an alarm signal, notify the MCU, and end this detection process, waiting for the next pulse signal from the MCU, so as to start a new round of detection process.

3. Software of Ultrasonic Flaw Detection System

In the entire digital ultrasonic flaw detection system, software design plays an important role. For this purpose, assembly language and VB high-level language are used to program MCU and PC respectively. The entire software system includes the main working interface and parameter setting interface. Among them, the working interface mainly includes: gain/compensation, sound path/scale design suppression/sound velocity, gate design DAC curve fitting, echo waveform display defect recording, defect playback, defect report printing, and data communication with PC. The parameter setting interface mainly includes: probe setting, instrument design, channel setting, password setting and clock calibration.

When the transmission frequency of the ultrasonic probe is above 10MHz, sampling at the existing sampling rate (40MHz) is likely to cause the loss of the peak value of the echo signal. In the existing design, the bottleneck restricting the speed is mainly concentrated on transferring the sampled echo signal value to the external RAM. Due to the restriction of RAM speed, it is difficult to further increase the operating frequency of the entire system.