Design and implementation of MⅢ bus conversion board based on FPGA and RS422

Airborne data bus technology is one of the most important key technologies for the integration of modern advanced aircraft fly-by-wire control systems and avionics . It is the specific implementation of computer network technology at the bottom of avionics, and determines the performance of aircraft and the degree of integration of avionics systems. This book introduces the basic technology of airborne data bus from two aspects: the basic technology of data bus and the seven-layer reference model of computer network OSI. It comprehensively analyzes the technical characteristics, protocol specifications, topology and communication interface design methods of ARINC-429, AmNC-629 and CSDB airborne data buses used on civil aircraft, and MIL-S1D-1553B, MIL-STD-1773, STANAG3838/3910 airborne data buses used on military aircraft, linear token passing bus LTPB , fiber optic distributed data interface FDDI and scalable interconnect interface SCI in avionics unified network, fiber channel FC, and the latest full-duplex switched Ethernet AFDX, and gives typical application examples.

The conversion card adopts the top-down design method and integrates the embedded configurable microprocessor technology to modularize the system. The top module adopts the graphical design method, and the bottom module is described by VerilogHDL language, and the simulation and synthesis are completed by Quartus lI, and then implemented on the Cyclone II series EP2C40 chip of ALTERA . This design improves the processing speed and stability of the system and reduces the power consumption and cost of the system.

1 Introduction to MIII Bus

The MIII bus is a dedicated data communication bus for certain aircraft fire control electronic equipment, also known as the third-level bus. The MIII bus is a unidirectional address, bidirectional data, half-duplex communication bus.

The logical relationship between the interface logic signal and the electrical signal of the MIII bus is: logic "1" corresponds to a logic high level; logic "0" corresponds to a logic high level.

MIII bus interface Signal line According to the function, it can be divided into three groups, namely data communication bus, address communication bus and signal control bus. Among them, the data communication bus includes 0pKlK2~15pKlK-2; address communication bus: 0pAl~15pAl. The "input" of the bus means the output of digital signs from the MIII bus conversion board to a certain aircraft fire control device, and the "output" means the input of digital signs from a certain aircraft fire control device to the MIII bus conversion board. The A1 address strobe of MIII is mainly used to track address data and select devices, and the external write strobe is used for digital tracking when transmitting data and addresses from the MIII bus conversion board to a certain aircraft fire control device. The external receive strobe is used for digital tracking when transmitting data from a certain aircraft fire control device to the MIII bus conversion board.

2 RS422 communication protocol

At present, the common serial communication interface standards are mainly RS 232, RS 422 and RS 485. RS 232 is a single-ended unbalanced transmission protocol with short transmission distance and poor anti-interference performance. RS 485 and RS 422 are both balanced communication interfaces, but RS 485 has only one pair of twisted pairs and works in half-duplex mode. RS 422 is a balanced communication interface that uses full-duplex communication mode, with a transmission rate of up to 10 Mb/s and a transmission distance of 2,000 m. It also allows up to 10 receivers to be connected on a balanced bus [1]. Due to the excellent performance of this type of circuit, RS 422 interface chips have been widely used in many fields such as industrial control, instruments, meters, multimedia networks, and mechatronics products.

3 Overall design of conversion board

The overall structure of the MIII bus conversion board is shown in Figure 1, which consists of an interface level conversion circuit, a bus interface control logic, a dual-port memory , and an RS422 conversion module. The bus interface control unit is mainly used for receiving and sending addresses and data, as well as for generating interface control signals and drive signals; the dual-port memory RAM is used to store data and addresses, including data sent by the MIII bus and data and addresses sent by the PC to the MIII bus; the interface level conversion circuit consists of a unidirectional drive circuit chip, which is used to provide a drive level signal that meets the requirements of the MIII bus.

3.1 Bus conversion design logic

In the design and development of the bus interface control unit, under the strict implementation of the national military standard for the development of ground equipment and other requirements, in order to ensure the reliability of the system, improve the scalability and performance of the system, and use mature technologies and devices as much as possible.

Based on the above design principles, the hardware circuit of the MIII bus interface board should be implemented using FPGA devices. FPGA (Field-Programmable Gate Array) is a field programmable gate array , which is a further development of programmable devices such as PAL, GAL, and CPLD . It appears as a semi-custom circuit in the field of application-specific integrated circuits ( ASICs ), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable devices.

The design starts from the overall system, applies Ouartus II software, and adopts structured description to analyze the functional characteristics of the design object. Then, the problem is gradually refined from top to bottom, and the functional modules are divided according to the analysis results. According to the circuit function, the data flow of each module circuit is described using Verilog HDL language, and then the function of each module is simulated by Quartus II software. Then, the modules are connected for logic synthesis and optimization, and finally downloaded to the FPGA chip.

3.2 RS422 conversion module

This module uses the SP3490 chip for RS422 communication protocol conversion. The SP3490 is a series of + 3.3V low-power full-duplex transceivers that fully meet the requirements of RS-485 and RS-422 serial protocols. These two devices are pin-compatible with Sipex SP490 and SP491 , and are compatible with common industrial standard specifications. SP3490 and SP3491 are manufactured using Sipex's BiCMOS process, which enables low-power operation without compromising performance. They comply with the electrical specifications of RS-485 and RS-422 serial protocols, and the data transmission rate can be as high as 10Mbps (with load). Figure 2 shows the circuit schematic of the RS422 conversion module.

3.3 Bus interface control unit

The main functions of the bus interface control unit are the reception, transmission, conversion, and storage of MIII bus addresses and data, as well as the generation of interface control signals and drive signals. SOPC is a special embedded system: first, it is a system on chip (SOC), that is, a single chip completes the main logic functions of the entire system; second, it is a programmable system with a flexible design method, which can be cut, expanded, and upgraded, and has the function of software and hardware programmable in the system. It uses programmable logic technology to put the entire system on a silicon chip for embedded system research and electronic information processing. SOPC is a special embedded system, which is a system on chip (SOC), that is, a single chip completes the main logic functions of the entire system, but it is not a simple SOC, it is also a programmable system with a flexible design method, which can be cut, expanded, and upgraded, and has the function of software and hardware programmable in the system.

(1) Nios II processor

The Nios processor is a second-generation on-chip programmable soft-core processor with a 32-bit instruction set. Its greatest advantage and feature is the modular hardware structure, as well as the flexibility and scalability it brings. Compared with traditional processors, the Nios II system can increase or decrease the number and types of peripherals according to actual needs during the design phase. Designers can use the development tool SOPC Builder provided by ALTERA to create a basic platform for software and hardware development on PLD devices, that is, use SOPC Builder to create a soft-core CPU and parameterized interface bus Avalon. On this basis, the hardware system (including processor, memory, peripheral interface and user logic circuit ) can be quickly integrated with conventional software in a single programmable chip. In addition, SOPC Builder also provides a standard interface method so that users can make their own peripheral circuits into peripheral modules that can be added to the Nios II soft core. This design method makes it easier to debug various systems. The Nios II processor unit generated by QuartusII software SOPC Builder is shown in Figure 3.

In specific operation, when the data flows from RS422 serial port to MIII bus, the NIOSII processor can read the data from the RS422 serial port receiving buffer memory and output it to the MIII bus sending buffer unit, and also send the data to the external SRAM for storage; when the data flows from MIII bus to RS422 serial port, the method is similar, the difference is that the transmission rate of MIII bus is much higher than the transmission rate of serial port.

(2) MIII bus transmission and reception

The MIII bus transceiver function is independent of the Nios system. It makes full use of the flexible configuration of FPGA and uses VerilogHDL language to implement the key parts of the MIII bus with high real-time and reliability requirements, and then simulates the logical functions of the MIII bus, and finally realizes the MIII bus data and address transmission and reception and communication with the Nios system through a custom interface. The signal timing of the MIII bus is shown in Figure 4.

The read and write timing of the conversion board can be described by VerilogHDL language, and then the finite state machine is used to implement the above operations, and the timing simulation is performed by Quartus II. The simulation waveform is shown in Figure 5.

3.4 Interface Level Conversion Circuit

Since the input/output level of FPGA programmable devices is usually 3.3 V, and the MIII bus device is connected to the OC gate input/output. The OC gate is also called the open collector circuit, and its internal voltage is +5 V. Therefore, the input/output of the FPGA needs to undergo two voltage conversions.

The first voltage conversion is to convert the FPGA input/output level of 3.3 V to 5 V. Since the data signal is bidirectional, and the address and control signals are unidirectional (sent from the MIII bus to the docking MIII bus device), the data signal should be converted by the 74LS245 chip, and the address and control lines should be converted by the 74LS244 chip. The circuit principle is shown in Figure 6.

Since the internal OC gate input/output of the MIII bus device is connected, and since the collector of the output tube of the OC gate circuit is suspended, an external pull-up resistor is required to be connected to the power supply when used . Generally, the OC gate uses a pull-up resistor to output a high level. In addition, in order to increase the driving ability of the output pin, the principle of selecting the pull-up resistor value is to reduce power consumption and the chip's current sinking ability should be large enough to ensure that the driving current is small enough. The specific level conversion circuit schematic is shown in Figure 7.

After the level conversion in the above two steps, the FPGA input/output signals can meet the input/output signal requirements of the MIII bus docking device. At this point, the MIII bus communication can be realized by simply sending and receiving the address, data and control signals input/output by the MIII bus conversion board according to the MIII bus timing.

4 Conclusion

This paper introduces the design method of the dedicated data communication bus (MIII bus) conversion board of a certain type of fire control electronic equipment, and gives the bus communication function of the MIII bus. At the same time, it introduces the implementation method of using F-PGA to realize part of the MIII bus circuit. In fact, the use of FPGA can simplify the system structure, shorten the design cycle, and improve the performance and scalability of the system. At present, the conversion board has been proven to be functional and stable after joint debugging with a certain type of fire control electronic equipment, and has been well received by users, and has received good social and economic benefits.