Structural Analysis and Implementation of Secondary Group Demultiplexer Based on FPGA

1. Introduction

In order to increase the transmission rate, expand the communication capacity and reduce the number of channels, multiple signals are usually multiplexed into one signal for transmission. Among the multiplexing methods, time division multiplexing is a common method. Time division multiplexing is a method in which multiple signals share one channel for transmission according to time intervals. Multiplexing is to combine multiple digital signals with relatively low rates into one signal through a certain protocol for transmission; while demultiplexing is just the opposite, which is to divide a signal with a relatively high rate into signals with relatively low rates corresponding to the sending end according to the corresponding protocol. In order to standardize the multiplexing and demultiplexing protocols, the ITU (International Telecommunication Union) divides the multiplexed digital signals into primary group, secondary group, tertiary group, quaternary group, etc. according to different levels of transmission rate. Taking the actual application in my country as an example, the rates are: 2.048MHz, 8.4.48MHz, 34.368MHz, 139.264MHz respectively. This article introduces the functions of the demultiplexing part of the secondary group digital signal based on FPGA, including frame header capture, frame loss alarm, primary group signal extraction, removal of insertion code, negative code rate adjustment and other key technologies of secondary group demultiplexing.

2. Introduction to the secondary group frame structure

The secondary group frame structure is shown in Figure 1. The frame length is 848 bits. The bit content of the multiframe is as follows:

(1) Frame alignment 10 bits, expressed as F11F12~F13F23, code type is 1111010000;

(2) 2 bits for official use, of which 1 bit (11 bits) is used to send an alarm indication to the other end; the other 1 bit (12 bits) is reserved for domestic use;

(3) Branch information: 820 bits, of which group 1 is 200 bits (13 to 212), group II is 208 bits (217 to 424), group III is 208 bits (429 to 636), and group IV is 204 bits (645 to 848);

(4) Code rate adjustment 4 bits, expressed as V1, V2, V3, V4 (641 to 644 bits), 1 bit for each base group, a total of 4 bits;

(5) Insertion flag 12 bits, represented by C, filled with 4 bits of pulse. In order to let the receiving end know whether there is an insertion and where it is inserted, the multiplexing end needs to send an insertion flag signal at the same time as the insertion command is issued to inform the demultiplexer that there is an insertion. The commonly used method at present is positioning insertion. Here it is stipulated that the first insertion flag C11 of the first group is inserted at the 213th position, the second insertion flag C12 of the first group is inserted at the 425th position, and the third insertion flag C13 of the first group is inserted at the 637th position. It can be seen from this that:

C11C21C31C41 is the first insertion flag;

C12C22C32C42 is the second insertion flag;

C13C23C33C43 is the 3rd insertion flag;

The insertion flag signal is 3 bits. Using a 3-bit code to form the insertion flag signal can improve the reliability of the flag signal. "111" indicates insertion, and "000" indicates no insertion. When C11C12C13 is "111", it means that the pulse in the 641 time slot is an insertion pulse; when C11C12C13 is "000", it means that the pulse in the 641 time slot is an information code.

A frame is divided into 4 groups, each with 212 bits. The allocation of these 212 bits is shown in Figure 2. The 4 groups are similar. Take the first group as an example. The 212 bits are divided into 4 groups, each with 53 bits. The 1st, 2nd, and 3rd code bits of the first group are used to insert the multiplexer frame synchronization code, represented by F; then there is the 50-bit information code; the first code bit of the II, III, and IV groups is used as a flag signal, represented by C; the second code bit of the IV group is the code bit for code rate adjustment, represented by V. When it needs to be inserted, a pulse without information is inserted at this position. When it is not necessary to insert, this code bit still transmits the information code; the other positions of the II, III, and IV groups are all information codes. The 1st to 3rd code bits of the 4 groups are multiplexed together, a total of 12 bits, of which the first 10 bits are used as the multiplexer frame synchronization code, the 12th bit is an alarm indication, and the 12th bit is used as a spare. The insertion flag signal code and the code rate adjustment bit of the 4 groups are connected together after multiplexing.

3. Secondary group frame header capture and frame loss alarm

According to the analysis of the secondary group frame structure above, the frame header signal code of the secondary group is: "1111010000" 10 bits. In FPGA, a 10-bit register is defined, and the secondary group signal code enters the 10-bit register from right to left. If the value of the 10-bit register is: "1111010000" twice in a row, it means that the frame header is captured successfully and frame synchronization is established. Similarly, if the frame header signal code is not captured within the time length of two consecutive secondary group frames, it means that the frame is lost and a frame loss alarm is generated. The VHDL language code implements the following program segment:

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4. Primary group signal extraction

A secondary group signal is multiplexed with four primary group signals. The primary group signal extraction is to convert the secondary group signal into serial-to-parallel signals according to the one-to-four rule under the state of secondary group frame synchronization. Because the secondary multiplexing is based on bit multiplexing, the first bit in a secondary group frame is the first bit of the first group, the second bit in a secondary group frame is the first bit of the second group, and so on. The VHDL language code implements the following program segment:

5. Remove insertion code and negative code speed adjustment

Removing the insertion code and adjusting the negative code rate are the key parts of the secondary group. First, remove F1, F2 and F3 inserted in the frame header; then remove C1, C25DC3; finally, determine whether the 161st bit V is an insertion code based on the values ​​of C1, C2 and C3. If C1C2C3 is: "1 11", then V is an insertion code and should be removed. If C1C2C3 is: "000", then V is the signal code of the primary group and should not be removed. Input the signal with the insertion code removed into a FIFO, and read the output primary group signal with a 2.048MHz clock adjusted by the negative code rate as shown in Figure 3.

Since the clock written to FIF0 is uneven, it is not conducive to back-end processing, so a negative code rate adjustment must be made, that is, the 2.112MHz rate is adjusted to the 2.048MHz rate. The principle of FPGA implementation is that the number of valid signal codes at the 2.112MHz rate and the 2.048MHz rate is the same, and adjustments can be made based on their number. If the signal codes output at the 2.048MHz rate are less, the frequency of the 2.048MHz clock is slightly increased. If the signal codes output at the 2.048MHz rate are more, the frequency of the 2.048MHz clock is slightly reduced.

The VHDL language code implements the following program segment: 1. Dynamically adjust the frequency of clk2048 according to the value of div to achieve negative code rate adjustment.

6. Conclusion

This paper proposes an FPGA-based solution for the secondary group tapping process, introduces the frame structure of the secondary group, and gives key VHDL language programs such as frame header capture, frame loss alarm, and negative code rate adjustment. It is compiled in QUARTUSII software, and the resources only occupy more than 30 LEs, which provides a reference for the design of secondary group equipment and has high application value.