Design of Power System Harmonic Analyzer Based on Dual DSP

This paper introduces a design of a power system harmonic analyzer based on dual TMS320F 28335. The analyzer can simultaneously realize the synchronous sampling of multi-channel signals (voltage and current) and perform harmonic analysis on them. With the help of the powerful dual TMS320F28335 platform, real-time analysis and display of signals are realized, with the advantages of good real-time performance, fast computing speed, high accuracy, good flexibility, and strong system expansion capability.

System Introduction

1 System Solution

Since the real-time requirements of this system are high and a large amount of data transmission and human-computer dialogue events occur during the working process, and the resources of a single DSP are limited, if a single DSP is used to process data, the system will not be able to process the sampled data in time and may cause some data loss, thus affecting the overall performance of the system. To make up for this shortcoming, this design proposes a dual-processor collaborative working mode of DSP+DRAM+DSP. One DSP is fully responsible for collection and capture, and the other is responsible for data processing and human-computer dialogue. This can achieve uninterrupted, high-speed, and multi-port processing. In view of the characteristics of mismatched speeds between the two communicating parties, high real-time requirements for information exchange, large amounts of information transmitted at one time, and accurate data transmission requirements, a comprehensive consideration of communication reliability, ease of implementation, and cost, etc., a dual-port RAM is used to achieve high-speed communication between multiple processors through a dual-machine interrupt interactive coordination mode. The overall block diagram of the system is shown in Figure 1.

Figure 1 System overall block diagram

2 Working process

First, the voltage and current on the PT (voltage transformer) and CT (current transformer) are converted into a follower-type AC low voltage through sensors, and then sent to the A/D module on the DSP chip after filtering through a two-stage RC filter. The dual DSP controls the A/D acquisition and data transmission, and finally the collected data is processed by various algorithms such as FFT to obtain the required various power grid parameters and judge the quality of the power. At the same time, under the control of external buttons, the data is displayed in real time on the LCD screen according to different commands, thereby achieving the purpose of real-time monitoring.

System hardware design

The hardware circuit of this power system harmonic analyzer mainly includes five parts: signal conversion module, signal preprocessing module, dual TMS320F28335 digital signal processing module, monochrome LCD screen module (CM320×240), and keyboard module.

1 Signal conversion module

The signal conversion module mainly includes the transformer and the program-controlled signal conditioning part. The transformer uses a precision voltage transformer (KV50A/P) and a current transformer (KT50A/P) with good high-frequency performance. The phase shift is less than 4-5°, and the signal frequency attenuation is less than 0.3-ldB at 2kHz, which can fully meet the accurate measurement of harmonics below 50. The program-controlled signal conditioning part uses the synchronous sampling method of the ADC on the TMS320F28335 chip to ensure that there is no relative phase shift between the voltage and current signals. Since the bipolar analog input signal cannot be directly input to the A/D module on the DSP-L chip, the SPI bus and GPIO port of the DSP-L machine on the dual DSP module control the attenuation/amplification ratio of the input signal to meet the A/D module's requirements for the input signal level (0-3V). The input signal conditioning part of the A/D module uses a 256-tap digital potentiometer AD5290 and a high-speed operational amplifier AD8202 to form a programmable signal amplifier/attenuator. The input characteristic of each input channel is 1MΩ input impedance + 30pF. The schematic diagram of the programmable signal conditioning circuit is shown in Figure 2.

Figure 2 Schematic diagram of programmable signal conditioning circuit

2 Signal preprocessing module

The signal preprocessing module mainly includes a fourth-order low-pass filter circuit and a synchronous square wave conversion circuit. According to the national requirements for harmonic measuring instruments, the frequency measurement range of Class A instruments is 0-2500Hz, so 128 points are sampled per cycle and per channel. According to engineering experience, a fourth-order Butterworth low-pass filter with a cutoff frequency of 1500Hz can achieve a good filtering effect. At the same time, in order to improve the measurement accuracy, the adaptive adjustment sampling interval technology is adopted, that is, it is automatically adjusted according to the frequency measured by the capture unit. This system uses a synchronous square wave conversion circuit to partially realize the frequency measurement. At the same time, in order to improve the common mode rejection ratio, the synchronous square wave conversion circuit uses an open-loop method to realize voltage comparison and input it to the in-phase end, and at the same time inputs a +1.5V comparison level at the inverting end, so that a square wave with a duty cycle of 50% can be obtained at the output end, that is, pin 6, where capacitor C5 plays a role in suppressing high-frequency noise. The synchronous square wave conversion circuit diagram is shown in Figure 3.

Figure 3 Synchronous square wave conversion circuit diagram

3 Dual TMS320F28335 digital signal processing modules

The dual 28335-DSP module is mainly composed of two TI C2000 series DSP-TMS320F28335 and one IDT70V28 (64K×16bit) dual-port RAM. The two DSPs are DSP-L and DSP-R respectively. The dual-port RAM adopts the mode of interactive coordination of dual-machine interruption to realize data sharing and transmission. The working sequence of the dual TMS320F28335 digital signal processing module is shown in Figure 4.

Figure 4 Dual TMS320F28335 CPU module operation

The specific steps of the interactive coordination of dual-machine interruption are as follows:

①The working cycle of DSP-L is generated by the interrupt of timer 1, and the working cycle is T4. At the beginning of each cycle, voltage and current are collected, and the collected data are continuously written to the dual-port RAM according to the ping-pong buffer structure. When a cycle is collected, an interrupt is sent to DSP-R, and the execution time of the interrupt is T1.

②After the DSP-R machine responds to the interrupt, it completes the software filtering algorithm and FFT algorithm to perform harmonic analysis and display the harmonic data on the LCD. The interrupt execution time is T2.

③DSP-L reads the command sent by the keyboard of R machine from the dual-port command area and adaptively adjusts the sampling interval according to the captured frequency measurement results, completes the sampling control of AD acquisition and completes the control of the programmable signal conditioning module of the digital potentiometer AD5290 through the SPI interface. The execution time of this interrupt is T3.

4 monochrome LCD screen modules

CM320240 is a graphic dot matrix LCD display, which mainly adopts dynamic drive principle. It consists of row driver controller and column driver controller to form a 320 (column) × 240 (row) full dot matrix LCD display. This display contains hardware font library, and the programming mode is simple and convenient.

The minimum read and write cycle of the LCD module is 800ns. If the bus mode is used to control the LCD module, the maximum read and write cycle of TMS320F2812 is 200ns, which cannot meet the requirements of the LCD module, so an indirect control method is used. In order to save hardware costs, this system uses general GPIO to control the read and write signals of the LCD screen.

5 Keyboard module

In order to meet the real-time requirements, this system uses key interrupts to complete the human-computer interaction function. The keyboard consists of six independent keys. When any key is pressed, the input of the INT13 pin jumps to a low level (INT13 is set to a falling delay trigger) to trigger the DSP external interrupt. After the CPU responds to the interrupt, it reads the keyboard status in the interrupt service subroutine and performs corresponding operations. The 6 keys are A phase voltage, B phase voltage, C phase voltage, A phase current, B phase current, and C phase current.

System software design

After the system is powered on, it bootstraps and loads the program according to the selected mode, jumps to the main program entry, initializes the relevant variables, data ping-pong buffer, command area, and control register, and enables XINTF and A/D timing sampling interrupts. After the timing interrupt is generated, the A/D inside the DSP-L machine starts sampling the 6 sets of sensor signals, and stores the conversion results in the ping-pong buffer, and then transmits the results to the DSP-R machine through the interrupt interactive coordination working mode. The DSP-R machine calls the FFT program to process these data and transmits the results to the LCD display in real time. It mainly includes three parts: data processing algorithm, keyboard interrupt subroutine, and display processing subroutine. The system dual-machine workflow diagram is shown in Figure 5.

Figure 5 System dual-machine workflow diagram

1 Data Processing Algorithm

The system mainly uses the following algorithms: ① low-pass filter processing algorithm; ② capture unit high-precision frequency measurement algorithm; ③ adaptive adjustment of sampling interval technology; ④ harmonic analysis of FFT algorithm. For specific algorithms and codes, please refer to the full version of this article on the website of "Today's Electronics".

2 Keyboard interrupt subroutine

In order to meet the real-time requirements of the system and complete the real-time response of keyboard operations, this system uses external interrupts to scan the keyboard to complete the command formation and flag setting functions. The keyboard interrupt subroutine flow chart is shown in Figure 6.

3 LCD display subroutine

The LCD display is divided into two parts: the information area and the display area. The information area includes fixed information (displaying Yantai University DSP Laboratory, etc.), and the display area includes the display of each phase frequency value and harmonic waveform.

Experimental Results

The sampling frequency of this system is fs=6400 Hz. The frequency measurement results of the capture unit and the amplitudes of each harmonic obtained by the FFT algorithm are shown in Table 1 and Table 2 respectively.

Error analysis

After analyzing the above parameters, it can be seen that when the frequency is about 50Hz, the maximum error does not exceed 0.01Hz, and the 19th harmonic of the harmonic analysis shows that the higher the wave order, the smaller the amplitude, and the amplitude of each harmonic is more in line with the actual situation. Since this system uses adaptive adjustment of sampling interval technology to achieve synchronous sampling, the measurement accuracy of the parameters is guaranteed.

Conclusion

This paper introduces a power system harmonic analyzer, which adopts a dual processor collaborative working structure of DSP+DRAM+DSP, and quickly communicates with the dual machines through the interactive coordination mode of dual machine interruption, which can meet the requirements of high-speed data acquisition and transmission. Due to the use of synchronous sampling technology, adaptive adjustment of sampling interval technology and zero-filling anti-spectrum leakage technology, it can achieve more accurate harmonic analysis, facilitate engineering applications, and has great practical application value.