A Low-Power-Aware FPGA Design Approach for Portable Products

ILGOO series low power FPGA products

Actel's ILGOO series devices are low-power FPGA products and are the best solution to replace ASIC and CPLD in portable product design. Its static power consumption in Flash*Freeze mode can reach as low as 2µW, and the battery life is more than 5 times that of products using mainstream PLDs. For low-power applications with a larger number of I/O requirements, Actel can provide the IGLOO PLUS series, with sizes of 30,000, 60,000 and 125,000 gates respectively. Compared with IGLOO devices in the same package, it can provide up to 64% more I/O. All its devices support 4 I/O banks. It is more advantageous in multi-voltage application environments and supports hot swapping and Schmitt triggers. In the development of the IGLOO series products, Actel has made improvements to the leakage current, the main physical source of static power consumption. At the same time, the yield, speed and reliability are strictly monitored during the production process.

Where does the low power consumption advantage of IGLOO devices come from? First of all, it comes from the control of the leakage current source by the IGLOO device itself, as well as the implementation of various power-saving features and various minimum power consumption data storage technologies provided by the device. In addition, some low-power techniques are used in the design to reduce static power consumption.

IGLOO has a power-friendly device architecture that provides static, sleep, and Flash*Freeze power modes, allowing the use of dynamic voltage and frequency adjustment technology to reduce the overall actual power consumption of the system. It provides selectable 1.2V and 1.5V I/O and core voltages to facilitate users to balance the relationship between design performance and power consumption. IGLOO's clock structure can gate global and local signals without side effects. In addition, IGLOO's RAM module has LP and F*F ports to control the static power consumption of the RAM itself.

System temperature and power consumption overview

Industrial, automotive electronics, military, and even commercial customers have regulations on the temperature and operating mode of the system. These profiles guide us where to pay attention and how to allocate energy during design. The low-power process and silicon design of IGLOO devices are guaranteed by Actel. What users need to pay attention to is: caring about the selection of devices, mastering the architecture of the FPGA used, and mastering the board-level layout of the PCB (mainly capacitors and I/O routing).

For the same series of devices, the smaller the die, the lower the power consumption. In other words, when selecting devices, you should try to choose small devices. After selecting the device, you can use some techniques to occupy as few resources as possible during the design process, such as using time-division multiplexing to occupy less I/O, sharing addition, multiplication and other algorithm logic, sharing RAM, etc. It is also necessary to understand the architecture of the selected FPGA.

Users need to strike a balance between power consumption and speed. When speed performance is not required, try to use low core voltage and low-voltage I/O interface standards. Depending on the actual design situation, sometimes turn off the resources that are not currently working, such as controlling the LP or BLK pins of the SRAM so that it can be turned off when not working, or enter the Fresh Freezee mode through the Flash Freeze port to reduce static power consumption. When the PLL does not need to work, turn it off through the Power Down pin, but it should be noted that it is necessary to consider whether the PLL lock time will affect the system after it is reopened. Turn off the I/O Bank without input bus.

Be careful not to abuse the pull-up/pull-down resistors. In active mode, if the bus is driven in reverse mode (such as a pull-up driven by a "0", or a pull-down driven by a "1"), the current on each I/O will increase. Be careful to prevent the driven bus from entering a 3-state state. Unless the FPGA's operating time is truly short, it is recommended to communicate with the board designer to ensure that the inputs are driven continuously.

To reduce the dynamic power consumption of a design, we must first understand the factors that affect dynamic power consumption. Dynamic power consumption is usually positively correlated with voltage, signal flip frequency, and capacitive load. The more logic resources a design occupies, the higher the clock frequency, and the more I/O and RAM, the greater the dynamic power consumption. At the same time, it is also necessary to analyze the dynamic power consumption profile of the design.

Determine the target of dynamic power reduction. If the target is to reduce dynamic power consumption by 20% of the current system dynamic power consumption, then Actel's IGLOO device may be able to achieve the target. If the target is 80%, in addition to using IGLOO devices, it is also necessary to consider the system and architecture.

For the overview of different system power consumption, the key points of dynamic power consumption are sorted out, as shown in Figure 1. For the schematic diagram of dynamic power consumption in Case 1, we can see that its power consumption is mainly distributed in logic, storage and clock. In this way, our energy cannot be focused on how to reduce I/O power consumption. For Case 3, if we want to reduce dynamic power consumption, we must solve the power consumption problem on I/O.

Figure 1 Highlights of the online discussion on dynamic power consumption of different systems [page]

To reduce RAM power consumption, in addition to gate control of RAM control and clock signals, it is also necessary to know how much RAM reading and writing affect power consumption, address changes, read and write sequence, and RAM cascade mode.

The read operation of RAM involves ten related circuits: controlling the stored address and control latch, row pre-decoding circuit, read column decoding circuit, row final decoding circuit, read column decoding control, sensor amplifier , data output selection and latch circuit, sense enable logic, read control circuit, Bit-line pre-charge circuit, etc. The write operation of RAM involves the following circuits: address and control latch, row pre-decoding circuit, write column decoding circuit, row final decoding control, write column decoding control, write drive circuit and Bit Line pre-charge circuit. Therefore, in comparison, the read operation consumes more power than the write operation.

The way the RAM read and write addresses change will also have different effects on power consumption. The smaller the Hamming distance between consecutive operation addresses, the less power consumption will be generated. And vice versa. In other words, the fewer the number of bits that change between the current operation address and the last operation address, the less power consumption will be generated.

Compared with continuous read and write operations, read-write interval operations consume more power. From the test results of 12 RAM blocks, 16 RAM blocks, and 24 RAM blocks in Figure 2, under the same operating conditions, the more RAM blocks there are and the longer the Hamming distance between consecutive operation addresses, the greater the power consumption. For the same number of blocks and the same Hamming distance between consecutive operations, writing and reading three times consumes more power than writing three times and reading three times.

Figure 2: Write-read sequence vs. read sequence followed by write sequence

As mentioned above, we can reduce the power consumption of RAM by adjusting the access order of RAM. If possible, perform fewer read operations on RAM, read or write more data at a time, and switch less between read and write operations. It is better if the Hamming distance between the addresses of consecutive identical operations can be kept to a minimum. You can also consider reading and writing RAM on the reverse clock edge to reduce the peak power consumption of RAM.

Different RAM cascade architectures generate different power consumption. If you want to get a 4K×4 RAM, there are many different implementations. As can be seen from Figure 3, according to these different implementations, the power consumption generated by gate control for each RAM read and write clock control is the lowest.

Figure 3 Root clock vs. leaf clock vs. gated enable [page]

In terms of reducing the power consumption of the clock tree, common methods include using gated clocks, modifying the commonly used pipeline clock structure, and using the global clock resources inside the FPGA as much as possible. By modifying the commonly used pipeline clock structure at the RTL level, as shown in Figure 4, the positive and negative clock edges are spaced, so that the clock frequency can be slowed down by half, which can save half the power consumption of the clock path. The power consumption generated by the clock tree can also be reduced by manually performing a planar layout of the clock domain. This method has relatively high requirements for engineers. Actel's designers provide a layout and routing strategy based on power consumption drive. Selecting this strategy, the layout and routing tool will automatically reduce the layout power consumption as much as possible while meeting the timing requirements.

Figure 4 Modification of the commonly used pipeline clock structure at the RTL level

To reduce the power consumption of logic and routing, you need to adjust the synthesis options, understand the architecture and power consumption profile of the algorithm/functional block, and reduce power consumption by reducing signal flipping. Different synthesis options and strategies will have an impact on dynamic power consumption. Basically, you need to pay attention to the global timing settings and the set_max_fanout option, as well as whether to use an area-first or timing-first synthesis strategy.

By evaluating the power consumption of DesignWare and some private adders at different frequencies, the BK adder under DesignWare is the most power-friendly. For the same 5% to 10% speed degradation, the BK adder can reduce the area and power consumption by 10% to 15% compared with other private adder cores. When selecting a multiplier, the area, power consumption and speed of the multiplier must be considered.

Counters have different uses in design. Some are used to calculate the order of events or the time spent, some are used to drive the address bus, data bus, next jump state of the state machine or output logic similar to RAM, and some are used to perform different set processing when the output value reaches different decoding values. Depending on the different uses, you can consider using binary sequential counting, Gray code counting, and ring counting. If the counter is only used to generate some marks, it is recommended to use a binary implementation; if the counter is used to drive a large load bus, it is recommended to use a Gray code counter; if the values ​​of multiple counters need to be decoded, a ring counter is the best choice (the decoding logic is minimal).

Reduce dynamic power consumption by reducing the toggle rate of logic

First of all, in the design, unnecessary flips need to be avoided as much as possible. This goal can be achieved through the following steps: first analyze which logic flips are unnecessary, then limit the propagation of unnecessary logic flips, and expand the time of logic flips.

To reduce the glitches that may be generated by logic, first identify the networks with high flip-over rates and their drivers, then evaluate the worst timing of the input of the driver unit, then adjust the source of the glitch forward or backward, and then evaluate the worst timing of the input of the driver unit, and finally insert a trigger after the driven logic. According to the previous evaluation, decide to drive the trigger with the same clock edge or the opposite clock edge of other timing elements on the path. Even on a single-cycle path, if there is enough slack to add an AND gate and related routing, then the inverted clock edge of the other input of the AND gate (the glitch source driving register) can be used to reduce the glitch. In some cases, the peak power consumption of the glitch can be reduced by stretching the reversal time.

It is recommended that designers understand the operating mode of the final system and the power consumption profile of the system in each mode. If the system is in sleep mode or shutdown mode for a long time, it is necessary to observe the impact of inrush current and programming current, and deal with static power consumption. It is necessary to check the dynamic power consumption profile of the design, find out the main bottleneck of power consumption, and find the best solution according to the summary table (Figure 5~Figure 8).

Figure 5 RAM dynamic power consumption summary table [page]

Figure 6 I/O power consumption summary table

Figure 7 Clock tree power consumption summary table

Figure 8 Logic power consumption summary table

Before comparing the summary table, you can modify the RTL code as long as the timing allows; ensure the functional and timing validity after the modification; you can also try to adjust the synthesis options and use a power-first strategy for layout and routing.