Design of high-precision phase measurement instrument based on FPGA

introduction

With the development of integrated circuits, it has become an effective method to use large-scale integrated circuits to complete the design of various high-speed and high-precision electronic instruments. The electronic instruments made using this technology have simple circuit structures, reliable performance, accurate measurements, and are easy to debug. This paper uses the Altera Cyclone II series FPGA device EP2C5 to design a high-precision phase measuring instrument. The signal source required to measure the phase difference is generated inside the FPGA using the DDS principle, and then the distance between the zero crossing points of the two sine waves is calculated through a high-speed clock pulse. Finally, the final phase value is obtained through a certain calculation circuit, and the phase measurement accuracy is 1°.

System hardware design

The hardware of the FPGA-based phase measurement instrument includes FPGA, high-speed DAC, voltage comparator, etc. Its system hardware structure is shown in Figure 1.

Figure 1 Phase measurement instrument hardware structure diagram

The measuring instrument presets the frequency and phase of the sine wave by pressing buttons. The frequency control word and phase control word required for the sine wave are calculated and generated through the control module inside the FPGA, and then the control word is input into the DDS module to generate waveform data output, and two sine waves are output through the 10-bit high-speed DACTHS5651. When measuring the phase difference, the phase-shifted sine wave output in Figure 1 is divided into two paths, one of which is directly input into the phase measurement module after being shaped by the voltage comparator LM311; the other path first passes through the circuit under test, and then is shaped by the voltage comparator and input into the phase measurement module, thereby obtaining the phase shift generated by the sine wave after passing through the circuit under test.

Hardware circuit design based on FPGA

Design of DDS Phase Shift Signal Source

The basic principle of DDS is to use the sampling theorem to generate waveforms through a table lookup method. The phase-shift signal generation module of this system is shown in Figure 2.

Figure 2 Block diagram of digital phase shift signal generation module based on DDS

In Figure 2, the adder and register are cascaded to form a phase accumulator. The phase accumulator is triggered by a clock pulse, so that the frequency control word is continuously accumulated. When the phase accumulator overflows once, it completes a periodic action, and this period is a frequency period of the DDS synthesized signal.

The data output by the phase accumulator is used as the phase sampling address of the waveform memory, and the waveform sampling value stored in the waveform memory is found through the lookup table, thereby completing the phase to amplitude conversion. Then the output of the waveform memory is sent to the DAC, and the waveform amplitude in digital form is converted into an analog waveform of the synthetic frequency through the DAC.

In Figure 2, FWORD is a 10-bit frequency control word; PWORD is a 10-bit phase shift control word, which is used to control the phase shift of the sinusoidal signal output; SINROM is used to store sinusoidal wave data, with 10-bit data lines and 10-bit address lines. The data file is a MIF file (data depth 1024, data type is decimal), which can be generated by Matlab, and the unit storing data is generated by custom ROM method; POUT and FOUT are both 10-bit outputs, respectively connected to two high-speed DACTHS5651. [page]

Control module generation

In the process of generating waveforms, the frequency and phase control words required by the DDS module are given by the control module written inside the FPGA. The top-level principle block diagram of the control module is shown in Figure 3.

Figure 3 Top-level block diagram of the control module

In FIG3 , B1, C10, D100 and P1K are frequency step input terminals respectively; Re is a reset terminal; PW1 and PW10 are 1:10:1 input terminals respectively; bcout is a frequency control word calculation module, which completes the conversion from frequency step value to binary frequency control word.

cout360 is the phase input calculation module, which calculates the actual phase shift value (0麀359) from the pulse input of the phase input terminal. add_data_rom is the ROM that stores the phase control word. Its data file is a MIF file. The 360 ​​internal address values ​​correspond to 0麀359南辔, and the data in each address is the address value of the sine wave ROM corresponding to each phase value. Since the sine wave ROM divides a waveform into 1024 points, 0麀359南辔恢刀杂α薙INROM. Considering that 1024/360=2.84 is not an integer, in order to reduce the phase shift error and improve the phase shift accuracy, this design adopts the segmented processing method to divide the 360 ​​addresses into 60 groups. The distance between the points in the 6 addresses of the 15th, 30th, 45th, and 60th groups is 3; the point distance between the first 5 points of the remaining groups is 3, and the point distance between the 5th and 6th points is 2.

Phase measurement module design principle

The phase measurement of this system adopts the method of measuring the distance between the zero crossing points of two waveforms by high-speed clock pulses. The principle block diagram of the phase measurement module is shown in Figure 4.

Figure 4 Principle block diagram of phase measurement module

In Figure 4, A and B are two square wave inputs, CLK is a 50MHz clock input, and the dfd2 block is a 2-way frequency division module triggered by the falling edge. The purpose of A and B being divided by 2 is to make the phase measurement range from 0麀180 to 0麀360. OR is an exclusive OR gate, and the pulse width of its output signal is (ba). clxw is a high-speed counter that calculates the length of (ba) through a 25MHz high-frequency clock. The fb360 module is a multiplication module that mainly completes the operation of (ba)×360. The bpsc module is a frequency division module that divides the 25MHz clock signal by (ba)×360 times, so that its output signal pulse width is Tclk×(ba)×360 (Tclk is a 25MHz clock period). xwc is a phase difference counting module. It calculates the length of Tclk×(ba)×360 through the A phase input pulse, and then completes the calculation of (ba)×360/a to obtain the phase difference output. At the same time, the module also sends the measured phase difference value to the digital tube display.

When simulating the module, the frequency was artificially set to 10KHz and the phase difference was set to 72.

System verification and debugging

In the verification of the entire system, the frequency and phase value of the waveform are set by the external buttons through the control module, and the waveform is generated by connecting the output terminals FOUT and POUT of the DDS module to the 10-bit DACTHS5651. By observing the two waveforms on the oscilloscope, it is found that the waveforms are relatively stable and the frequency is consistent with the set value. In addition, in order to measure whether the phase shift generated by the DDS module is correct, the phase shift value is manually set through the phase input terminal, and the waveforms output from the reference waveform output terminal and the phase shift output terminal are shaped, and the phase difference of the two waveforms is measured with the phase measurement module. Through hardware debugging, it is found that the measured phase difference is completely consistent with the set phase difference, which proves that the system is accurate and stable.

Conclusion

This system uses Altera's quartusII4.1 as the hardware development platform, and uses VHDL language for circuit design. In the design, the modules are divided according to their functions, which is convenient for debugging and modification, and easy to upgrade. At the same time, the system design also uses more synchronous timing circuits to realize the functions of each process module, thereby effectively avoiding circuit glitches. In addition, in the phase measurement module, the phase difference counting block also has a latching function, which is conducive to the stable display of the output phase difference value.