TSMC's 2nm plant's initial review was blocked due to incomplete information

According to Taiwan media China Times Electronic News, the Taiwan Environmental Protection Agency held a preliminary review meeting of the project team for the second phase expansion plan of the Baoshan land in the Hsinchu Science Park on the 16th, which included the reserved site for TSMC's 2nm factory.

However, after heated discussions, the EIA committee believed that there were still some contents that required additional explanation from the developer, and decided to re-examine the case after supplementing the information.

The Hsinchu Science Park Administration stated that since the first phase expansion plan of the Baoshan land is mainly for process research and development and early mass production, in order to maintain the leading position of the island's semiconductor industry, in response to breakthroughs in 3-nanometer and 2-nanometer processes in recent years, the existing factory buildings can no longer accommodate the new generation of machines and there is no suitable land in the park.

Image source: Tencent

TSMC has previously stated that its 2nm technology R&D and production will be carried out in Baoshan and Hsinchu, while further noting that it is planning to have four super-large wafer fabs covering 222 acres.

TSMC estimates that it will conduct small-batch risk experiments in 2023, and Apple, Qualcomm, Nvidia, AMD and others will become customers of its 2nm technology in the future.

Moore’s Law states that the number of transistors on an integrated circuit has doubled approximately every 18 months since the early 1970s. Eventually (probably not too long from now), Moore’s Law will end because it will no longer be possible to shrink the hardware any further.

Current chips have used FinFET, or fin field-effect transistors, since the 22nm process in 2011, which solves the problems caused by smaller transistors.

FinFETs were great until we got down to 5nm. When we get down to the atomic level (3nm is 25 silicon atoms in a row), FinFETs start to leak and may not work at higher process levels.

In the 2nm process, TSMC will abandon the FinFET (fin field effect transistor) that has been used for many years, and will not even use the GAAFET (gate-all-around field effect transistor) that Samsung plans to use in the 3nm process, that is, nanowire, but will expand it into MBCFET (multi-bridge channel field effect transistor), that is, nanosheet.