Interview with Andes Technology executives to explore the development path of RISC-V

Since the birth of RISC-V in 2010, it has attracted attention from all walks of life. Today, RISC-V appears more and more in technology news, and a large number of technology companies have joined RISC-V research and production. There is no doubt that the era of RISC-V is coming. However, in an industry with so many traditional architectures, how RISC-V can break through the monopoly of Arm and create its own world remains to be seen.

Recently, Andes Technology held a RISC-V CON in Beijing, which brought us the latest developments about RISC-V and its industrial ecosystem. The theme of this RISC-V CON focused on the latest market analysis of RISC-V, innovative technology applications and various solutions of RISC-V ecosystem partners, helping customers to launch innovative designs based on RISC-V ISA more quickly.

The conference started with an opening speech by Andes Technology General Manager Lin Zhiming, followed by a keynote speech by Dr. Zhang Ke, Director of the Secretariat of the China Open Instruction Ecosystem (RISC-V) Alliance and Senior Engineer of the Institute of Computing Technology of the Chinese Academy of Sciences. Then, Andes CTO and Executive Vice President Dr. Su Hongmeng and Director of the Solution Architecture Engineering Department Shi Jiahong introduced Andes' latest products and shared technical highlights. In the second half, Hex Five Security CEO Cesare Garlati, Silex Insight Embedded Product Security and Customer Support Engineer Christopher Beaver and Faraday Marketing Manager Kenneth Lu will share various solutions.

The two bigwigs expect RISC-V to reach a higher level

Mr. Lin Zhiming, General Manager of Andes Technology, the organizer of RISC-V CON, and Dr. Su Hongmeng, CTO and Executive Vice President of Andes Technology, were interviewed during the conference.

RISC-V market will accelerate, 2 billion is a node

The RISC-V industry ecosystem is entering a period of rapid development. Since the establishment of the non-profit RISC-V Foundation at the University of California, Berkeley in 2015, it aims to aggregate global innovation forces to jointly build an open and cooperative software and hardware community and create a RISC-V ecosystem. my country is also stepping up efforts to promote RISC-V and has established the China Open Instruction Ecosystem (RISC-V) Alliance (CRVA, hereinafter referred to as the "Alliance") and the China RISC-V Industry Alliance (CRVIC). Currently, more than 300 manufacturers around the world have joined the RISC-V Foundation and become its members.

Lin Zhiming said that the current market size is about 2 billion US dollars. In the future, more companies will invest in RISC-V under the promotion of the foundation. Judging from this trend, it will not be far away to reach a scale of 20-40 billion. It is unknown whether the development trend of RISC will rise like shared bicycles in the future. Dr. Su also said: "Over the years, we have been improving every generation since the first generation of RISC. With the increasing demand in the CPU field, Andes Technology will provide customers with good solutions with its rich experience."

It is understood that Andes Technology has always believed that the RISC-V processor core will successfully move towards commercialization, so it joined the RISC-V Foundation as a founding member very early. In addition to quickly grasping the RISC-V initiative, Andes's independent research and development results are also an important factor in its success. Since the RISC-V architecture has many similarities with the foundation of Andes' original CPU IP products, Andes immediately developed RISC-V's 32/64-bit processor core after the RISC-V Foundation officially released the specific instruction set architecture. Lin Zhiming said, "Currently, more than 150 companies have obtained the AndesCore™ processor IP license, and the cumulative global shipments of chips using Andes architecture have reached billions."

Why does RISC-V favor AI and IoT fields?

The application scope of RISC-V is gradually expanding, and the first to benefit are the fields of AI and IoT. It can be seen that AI, IoT, and robots will change the direction of chip technology research and technical research in the next three years, especially IoT has become the main driving force for the current development of science and technology. RISC-V is mainly aimed at the IoT industry. The RISC-V industry, which is in the process of exploding, will have an impact on ARM in the embedded markets such as consumer and IoT.

In response to this phenomenon, Dr. Su Hongmeng believes that the advantage of RISC-V lies in its design, which draws on the experience of X86 and ARM architectures. There is no need to repeat the pitfalls of predecessors. At the same time, there is no need to be backward compatible with old designs and outdated instructions. It is also very streamlined and has no historical baggage. A manual, a technical manual, RISC-V only needs a few hundred pages, while ARM and Intel are both 2,000 pages. It is relatively simple and the code is also small. Therefore, based on the simplicity and modularity of RISC, it is particularly suitable for diverse and small-scale IoT applications, allowing developers to directly start with the RISC-V CPU with a simple instruction set when designing SoC (system-on-chip), which meets the requirements of IoT products being just in place and taking into account cost savings. In addition, RISC-V allows developers to add and modify instructions, and can optimize for application areas, which is particularly suitable for AI computing.

Indeed, as Dr. Su said, the RISC-V architecture has the advantage of being a latecomer. Due to the years of development of computer architecture, it has become a relatively mature technology. The problems exposed in the process of continuous maturity over the years have been thoroughly studied. Therefore, the new RISC-V architecture can avoid them and does not carry the historical burden of backward compatibility. It can be said that it is free of problems.

The development of any new technology requires the support of an ecosystem. What is the ecological environment of RISC-V like?

As we all know, RISC-V is an open source instruction set architecture (ISA) with clear layers, modular design characteristics and scalability. Architects can add their own instruction sets based on the architectural rules and propose design features to the basic working group, which is something that Intel and ARM architectures cannot achieve.

Lin Zhiming said that the development of the RISC-V ecosystem has basically matured. At present, countries and regions including the United States and European countries have set off a RISC-V craze, and various companies in the RISC-V camp have gradually formed a cooperative situation. Previously, Andes Technology had its own CPU series and has been focusing on the development of the RISC-V architecture since 2015. It is relatively active in the RISC-V Foundation. At present, it has made initial progress in the global RISC-V CPU IP industry, and its product line ranges from relatively basic CPUs to mid-range Linux to 32-bit and 64-bit products such as DPA. With its relatively complete product portfolio, reliable RISC-V core IP suppliers, and ultra-low power consumption and high computing performance processor cores, Andes has developed RISC-V processor cores with customizable instructions for customers.

However, RISC still has its shortcomings. In Lin Zhiming's opinion, the design time of the chip is a major shortcoming. Based on the current technological development, it may take 2-4 years for the system chip to go from initial design to mass production. This is something that companies in all links need to work hard to break through.

RISC-V will start to do 'subtraction'

The characteristic of RISC-V instructions is simplicity. In the actual work of IC design, the simplest design is often the most reliable and has been tested again and again in most project practices. The nature of IC design work is very special. Its final output is a chip. The design and manufacturing cycle of a chip is very long. It cannot be easily upgraded and patched like software code. It takes several months for each chip revision to be delivered. Not only that, the one-time manufacturing cost of the chip is high, ranging from hundreds of thousands of US dollars to hundreds of millions of US dollars. These characteristics determine that the trial and error cost of IC design is extremely high, so it is very important to be able to effectively reduce the occurrence of errors.

Lin Zhiming said that in order to be more developer-friendly and focus on larger pipelines and vector expansion, RISC-V will start to do "subtraction" . The so-called subtraction refers to how to optimize CPU applications so as not to waste extra resources. The chips provided by Andes Technology have the characteristics of configurability and scalability, and will also provide tools for engineers to set instruction sets to achieve the best performance and the right level of efficiency. Andes also provides configurable platforms for customers, which can build unique system architectures and software and hardware divisions to obtain design optimization at all levels, so as to achieve the best solution for cost and performance for customers.

1. Andes' instruction set architecture: AndeStar™ ISA
2. Andes' embedded processor: AndesCore™ CPU
3. Andes' hardware development platform: AndeShape™ Platform 
4. Andes' software development platform and tool chain: AndeSight™ IDE
5. Andes' software support system: AndeSoft™ SW Stacks 

It is reported that Andes Technology is also working with multiple parties to strengthen the promotion of RISC-V. Recently, Andes announced a strategic partnership with Silex Insight, a leading security IP manufacturer with flexible options, to jointly launch a low-power, highly flexible root of trust complete solution based on Andes RISC-V CPU.

Silex Insight's advanced eSecure IP module is a complete solution for security applications that prevents confidential information from being leaked and provides secure boot, key authentication and application protection. AndesCore™'s high-performance, low-power, two-stage pipeline RISC-V CPU core N22 is tightly integrated with the eSecure module to fully and reliably control and execute security protection functions.

Although RISC-V has the advantage of open source, its security cannot be ignored. On November 13, Secure-IC, a French embedded security solution provider dedicated to embedded network security to block malicious attacks, announced that it has established a strategic partnership with Andes Technology, a founding member of the RISC-V Foundation and a leading supplier of 32/64-bit embedded CPU cores, which produces more than 1 billion diverse SoCs per year, to jointly launch secure and high-performance processors.

Andes RISC-V processor integrates Secure-IC's Cyber ​​Escort Unit™ to protect against physical and network attacks, including buffer overflow, error injection attacks, and instruction skipping or replacement, and complies with the Common Criteria for Security Evaluation High Level (EAL) certification and PP0084 Protection Profile certification. In addition, the solution is fully consistent with the System Security Integration of Hardware/Firmware (SSITH) program launched by DARPA.

Summary

Open source chips are an important trend in the future chip design industry. They essentially solve the efficiency problems of long chip design cycles and non-reusable designs. Once an open source project has enough support behind it, it can achieve good enough quality to be widely used and enter a positive cycle. RISC-V has open-sourced a series of IPs with instruction sets as the core, and has successfully established its own ecosystem with the help of the RISC-V Foundation. It is expected to be widely used in heterogeneous computing and IoT fields in the future. We hope to see more such high-quality open source chip projects in the future, which will bring new development directions to the chip design industry.

Andes Technology General Manager Mr. Lin Zhiming (right), Andes Technology Chief Technology Officer and Executive Vice President Dr. Su Hongmeng (left)