CHIPS Alliance Launches New Project Using Western Digital RISC-V Cores and FuseSoC Tools-EEWORLD

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Using Western Digital's open source SweRV core and FuseSoC tools, an open source project called SweRVolf was created.

The project was jointly promoted by Olof Kindgren, creator and maintainer of FuseSoC, as well as Zvonimir Bandic, technical director of next-generation platforms at Western Digital, Martin Fink, the outgoing CTO (as a long-time supporter of RISC-V and Western Digital CTO Martin Fink announced his upcoming retirement, Dr. Siva Sivaram of Western Digital will become the new president of technology and strategy, but Fink will continue to serve as an advisor on "data center architecture related matters (including RISC-V)".) and the CHIPS Alliance. SweRVolf is based on Western Digital's open system-on-chip core SweRV EH1 RISC-V.

"Our idea is to provide a portable and scalable SoC for FPGA and simulation to verify the SweRV EH1 core." Engineer Kindgren explained. "The initial target was the Digilent Nexys A7 FPGA board and simulated using Modelsim or Verilator. By using FuseSoC, it can be ported to other development boards more quickly."

"This also proves that the FOSSi Alliance is vibrant because it combines IP cores and tools from different developers and groups around the world to create a completely open source project that can be used in industry, academia or hobbyists. To give some examples, in addition to Western Digital's CPU, most of the AXI infrastructure comes from the PULP platform, DDR2 controllers from Enjoy Digital, OpenOCD integration from M Labs, and tools including lowRISC, FuseSoC, etc. "Kindgren said that

the full name of the FOSSi Alliance is Free and Open Source Silicon. The core concept of the alliance is to build a free and open chip platform.

The name of the CHIPS Alliance actually comes from the abbreviation of Common Hardware for Interfaces, Processors and Systems, which is committed to providing more efficient and flexible chip innovation designs for network and terminal equipment. The initial member companies of the alliance include Google, WesternDigital, Esperanto and SiFive.

The CHIPS Alliance will continue to focus on open source hardware and the open RISC-V architecture. RISC-V is the fifth-generation open instruction set architecture based on the principle of reduced instruction set computing (RISC). It hopes to enter a new era of processor innovation through open source and collaboration.

Keywords：CHIPS SoC RISC-V FOSSi Reference address：CHIPS Alliance Launches New Project Using Western Digital RISC-V Cores and FuseSoC Tools

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