FPGA+CPU: Parallel processing is popular-EEWORLD

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In the deep submicron era, traditional materials, structures and even processes are reaching their limits, and Moore's Law is already somewhat stretched. Entering the deep subnanometer era, the size of transistors will be close to that of a single atom and cannot be reduced any further. Traditional ASIC and ASSP designs inevitably encounter problems such as complex design processes, reduced production yields, long design cycles, and a sharp increase in R&D and manufacturing costs, which to some extent have greatly slowed down the continuation of Moore's Law.

　　It is obvious that facing the huge tape-out costs, many small and medium-sized companies have to change their strategies and turn more to FPGA development and design. Looking at the FPGA market, even five years ago, its market growth rate was still quite slow compared to ASIC, but in recent years, especially after entering the 90nm node, its cost advantage has gradually become prominent.

　　For 20 years, Xilinx and Altera, the two giants that have long dominated the programmable logic device market, have been making frequent moves. In August, Altera held a seminar and a technical tour in 13 cities, vigorously promoting V series products on the 28nm process, the transition from SOPC Builder to the new Qsys platform, and even the new concept of SOC FPGA. In contrast, Xilinx was much more low-key in September, but still took out the 7 series products to challenge its competitors. From 65nm a year ago to 28nm today, since gate delay is no longer a bottleneck for speed performance improvement, the only change that users can feel is the increase in device density and the decrease in unit cost. In addition, it can only be said that manufacturers racking their brains to optimize device architecture and improve development tool performance has become another landscape to watch.

　　Coincidentally, Xilinx and Altera have accelerated the launch of FPGA devices with embedded hard-core CPUs. The FPGA+CPU solution is not uncommon. It was proposed and put into practice as early as five years ago. Xilinx and Altera have also been committed to the promotion of their own soft-core CPUs, but the market response has obviously not met expectations. In response to market demand, Xilinx took the lead in releasing the Extensible Processing Platform architecture integrating ARM Cortex-A9 CPU and 28nm FPGA in April last year. Less than a year later, the extensible processing platform Zynq-7000 series has been brought to the forefront again, which shows Xilinx's good intentions. Altera is not to be outdone. Intel integrated Altera's FPGA into the Atom E600C configurable processor released last fall, and Altera's upcoming SoC FPGA, which also integrates the Cortex-A9 CPU, is obviously intended to compete with Xilinx.

　　For us, we need to explore and think whether this new development platform can really meet the growing "material culture" needs of customers. We can't help but ask: Is the FPGA+CPU integrated architecture in line with the trend of historical development, or is it just a flash in the pan?

　　As shown in Figure 1, a relatively simplified traditional embedded system is shown on the left, and the FPGA architecture with a single integrated CPU is shown on the right. From the perspective of hardware architecture alone, it does not seem to have much advantage, it is just two-in-one. However, engineers who have actually done system development know that this two-in-one brings not only BOM cost reduction and layout simplification, but also more benefits such as optimization of the underlying connection between software and hardware that is invisible to the naked eye, and the invisible flexibility and potential performance improvement.

　　figure 1

　　Some potential advantages of FPGA-based CPU integration include: easier to meet the functional requirements of most systems; potential improvement in system performance; greatly improved flexibility and upgradeability in certain applications; optimized processor-to-peripheral interface; greatly improved interface performance for hardware and software interconnection; conducive to design reuse and rapid prototyping of new designs; and simplified PCB layout and routing for single chips or even entire boards.

　　The advantages of FPGA+CPU monolithic integration over traditional applications are evident from this, but from another perspective, just as the evolution of CPU from single-core to multi-core is continuing the "curse" of Moore's Law, the strong attack of FPGA+CPU is more like the popularity of parallel processing in embedded applications.

　　Continuing their usual style, Xilinx and Altera have both chosen the excellent ARM Cortex-A9 core for their CPU-embedded FPGA devices, which shows that they are currently targeting the mid-to-high-end application customers. As for low-end applications, even in the era of Internet explosion, the obscure Capital-Micro company is still not well known to the majority of engineers, but the reconfigurable system chip CsoC (Configurable SoC) they developed has quietly carved out a bloody path in the mid-to-low-end market applications. It is worth mentioning that this is a genuine Chinese local FPGA manufacturer.

　　It has been exactly 40 years since Intel's first 4-bit processor was launched in 1971. Although the embedded industry has undergone tremendous changes, even if you think it is "rustic" but simple and practical, the 8-bit MCS-51 microcontroller is still unique, especially in the entire domestic industrial control industry. Since its establishment in 2005, Capital-Micro has successively launched two generations of CSoC, Astro and AstroII. Its embedded 8051 can run stably at 100MHz and 150MHz on the two generations of devices respectively. Although the FPGA manufacturing process is still at 0.13um, which greatly restricts the logic performance, the current two generations of products can at least meet the industrial application needs including stepper motor control, LCD drive control, interface expansion, LED control card, and micro printer.

　　From the internal architecture of the device, as shown in Figure 2, AstroII not only has the 8051 hard core with "excellent" performance among similar products, but also integrates some common peripherals such as timers, watchdogs, UARTs, IICs and SPIs. Of course, the program startup of 8051 also completely adopts a direct mapping (Fully Shadowed) method similar to many ARMs to ensure that the slow reading and writing of ROM no longer becomes a bottleneck restricting CPU performance. As for the interconnection between 8051 and FPGA, not only can the EMIF addressing of 8051 (23-bit wide addressable address bus) be used, but the 4K×8bit DPRAM is also a good choice for high-speed data transmission, and the synchronization logic has been solidified on these interconnection interfaces, without the need for designers to waste energy. In addition, from the cheapest crystal clock support to the maximization of the number of I/Os, to its affordable price, all show us the "economical and practical" nature of this domestic chip.

　　figure 2

　　In a word, no matter it is Xilinx, Altera, or the emerging Capital-Micro, the new monolithic integrated devices they promote all indicate that the parallel processing architecture of FPGA+CPU will open up a brand new world in embedded applications. In this deep sub-nanometer era where the performance improvement of single chip is about to reach its limit, the flexible and changeable FPGA will surely help the performance of traditional CPU to reach new heights again with its unique parallelism.

Keywords：FPGA Reference address：FPGA+CPU: Parallel processing is popular

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