A must-read for beginners of DSP

Can DSP be used at a reduced frequency? 
Yes, the main frequency of DSP digital signal processing has a certain operating range, so DSP can be used at a reduced frequency. 

How to choose an external clock? 
The internal instruction cycle of DSP is high, and the main frequency of the external crystal oscillator is not enough, so most DSP chips have PLL. But each series is different. 
1) TMS320C2000 series: 
TMS320C20x: PLL can be divided by 2, ×1, ×2 and ×4, so the external clock can be 5MHz-40MHz. 
TMS320F240: PLL can be divided by 2, ×1, ×1.5, ×2, ×2.5, ×3, ×4, ×4.5, ×5 and ×9, so the external clock can be 2.22MHz-40MHz. 
TMS320F241/C242/F243: PLL can be ×4, so the external clock is 5MHz. TMS320LF24xx: PLL can be adjusted by RC, so the external clock is 4MHz-20MHz. 
TMS320LF24xxA: PLL can be adjusted by RC, so the external clock is 4MHz-20MHz. 
2)TMS320C3x series: 
TMS320C3x: No PLL, so the external main frequency is twice the operating frequency. 
TMS320VC33: PLL can be ÷2, ×1, ×5, so the external main frequency can be 12MHz-100MHz. 
3)TMS320C5000 series: 
TMS320VC54xx: PLL can be ÷4, ÷2, ×1-32, so the external main frequency can be 0.625MHz-50MHz. 
TMS320VC55xx: PLL can be ÷4, ÷2, ×1-32, so the external main frequency can be 6.25MHz-300MHz. 
4)TMS320C6000 series: 
TMS320C62xx: PLL can be ×1, ×4, ×6, ×7, ×8, ×9, ×10 and ×11, so the external main frequency can be 11.8MHz-300MHz. 
TMS320C67xx: PLL can be ×1 and ×4, so the external main frequency can be 12.5MHz-230MHz. 
TMS320C64xx: PLL can be ×1, ×6 and ×12, so the external main frequency can be 30MHz-720MHz

How to choose the external memory of DSP? 
DSP is fast. In order to ensure the running speed of DSP digital signal processing, the external memory needs to have a certain speed, otherwise the DSP needs to add a waiting cycle when accessing the external memory. 
1) For C2000 series: C2000 series can only be directly connected to asynchronous memory. The current maximum speed of C2000 series DSP is 150MHz. Recommended memories are: 
CY7C199-15: 32K×8, 15ns, 5V; 
CY7C1021-12: 64K×16, 15ns, 5V; CY7C1021V33-12: 64K×16, 15ns, 3.3V. 
2) For C3x series: C3x series can only be directly connected to asynchronous memory. The maximum speed of C3x series DSP is 40MHz for 5V and 75MHz for 3.3V. In order to ensure that DSP runs without waiting, the speed of external memory needs to be <25ns and <12ns respectively. The recommended memories are: 
ROM: AM29F400-70: 256K×16, 70ns, 5V, add one wait; 
AM29LV400-55 (SST39VF400): 256K×16, 55ns, 3.3V, add two waits (there is no faster Flash at present). 
SRAM: CY7C199-15: 32K×8, 15ns, 5V; 
CY7C1021-15: 64K×16, 15ns, 5V; CY7C1009-15 
: 128K×8, 15ns, 5V; CY7C1049-15 
: 512K×8, 15ns, 5V; 
CY7C1021V33-15: 64K×16, 15ns, 3.3V; 
CY7C1009V33-15: 128K×8, 15ns, 3.3V; 
CY7C1041V33-15: 256k×16, 15ns, 3.3V. 
3) For C54x series: C54x series can only be directly connected to synchronous and asynchronous memories. The speed of the C54x series DSP is 100MHz or 160MHz. To ensure that the DSP runs without waiting, the speed of the external memory is required to be <10ns or <6ns. The recommended memories are: 
ROM: AM29LV400-55 (SST39VF400): 256K×16, 55ns, 3.3V, add 5 or 9 waits (currently there is no faster Flash). 
SRAM: CY7C1021V33-12: 64K×16, 12ns, 3.3V, add one wait; 
CY7C1009V33-12: 128K×8, 12ns, 3.3V, add one wait. 
4) For the C55x and C6000 series: Among TI's DSPs, only C55x and C6000 can be connected to synchronous memory. Synchronous memory can ensure that the system data exchange efficiency is higher. 
ROM: AM29LV400-55 (SST39VF400): 256K×16, 55ns, 3.3V. 
SDRAM: HY57V651620BTC-10S: 64M, 10ns. 
SBSRAM: CY7C1329-133AC, 64k×32; 
CY7C1339-133AC, 128k×32. 
FIFO: CY7C42x5V-10ASC, 32k/64k×18.

How much driving power does the DSP chip have? 
The driving power of DSP digital signal processing is strong, and it can connect more than 8 standard TTL gates without adding a driver.

Commonly asked questions for debugging the TMS320C2000 series? 
1) Single-step operation is possible, but continuous operation always returns to address 0: Watchdog is not turned off, and continuous operation resets the DSP back to address 0. 
2) OUT files cannot be loaded into the on-chip flash: Flash is not RAM, and cannot be written with simple write instructions. A special program is required to write. The load command in CCS and C Source Debugger cannot write to flash. OUT files can only be loaded into on-chip RAM or off-chip RAM. 
3) How to add breakpoints in flash: You can use single-step debugging in flash, or you can use hardware breakpoints to add breakpoints in flash. Software breakpoints cannot be added in ROM. Hardware breakpoints set the address of the memory, and an interrupt is generated when the address is accessed. 
4) Interrupt vector: The interrupt vector of C2000 cannot be relocated, so the interrupt vector must be placed in the flash starting at address 0. When debugging the system, the code is placed in RAM, and the interrupt vector must also be placed in flash.

What are the common problems in debugging TMS320C3x series? 
1) TMS320C32 memory configuration: The program memory of TMS320C32 can be configured as 16-bit or 32-bit; the data memory can be configured as 8-bit, 16-bit or 32-bit. 
2) TMS320VC33 PLL control: The PLL control terminal of TMS320VC33 can only be connected to 1.8V, not 3.3V or 5V.

How to debug multiple DSPs? 
For DSPs with MPSD emulation ports (TMS320C30/C31/C32), you cannot use one emulator to debug at the same time. You can only debug one DSP at a time. For DSPs with JTAG emulation ports, you can connect JTAGs in series and use one emulator to debug multiple DSPs at the same time. Each DSP digital signal processing can be debugged with a different name in a different window. Note: If you add a driver between JTAG and DSP, you must use a fast gate circuit. You cannot use a slow gate circuit such as LS.

Why do we use CPLD in DSP systems? 
DSP is fast, so the decoding speed must also be fast. The decoding method using small-scale logic devices can no longer meet the requirements of DSP systems. At the same time, DSP systems often require the cooperation of external fast components, which are often specialized circuits implemented by programmable devices. CPLD has strict timing, fast speed, and good programmability, making it very suitable for implementing decoding and specialized circuits. 

What are the commonly used chips in DSP systems? 
1) Power supply: TPS73HD3xx, TPS7333, TPS56100, PT64xx... 
2) Flash: AM29F400, AM29LV400, SST39VF400... 
3) SRAM: CY7C1021, CY7C1009, CY7C1049... 
4) FIFO: CY7C425, CY7C42x5... 
5) Dual port: CY7C136, CY7C133, CY7C1342... 
6) SBSRAM: CY7C1329, CY7C1339... 
7) SDRAM: HY57V651620BTC... 
8) CPLD: CY37000 series, CY38000 series, CY39000 series... 
9) PCI: PCI2040, CY7C09449... 
10) USB: AN21xx, CY7C68xxx... 
11) Codec: TLV320AIC23, TLV320AIC10... 
12) A/D, D/A: ADS7805, TLV2543... 
 

What is a boot loader? 
DSP is very fast, EPROM or flash is slow, while the RAM inside the DSP is very fast and the RAM outside the DSP is also fast. In order for the DSP to fully exert its capabilities, the program code must be placed in the RAM and run. In order to conveniently move the code from ROM to RAM, TI solidifies a program in the DSP without flash before leaving the factory, which completes the move of the code from ROM or peripherals to the user-specified RAM after power-on. This program is called a "boot loader".