Dual-channel digital storage oscilloscope based on DSP

1. Introduction

　　Digital storage oscilloscopes are different from general analog oscilloscopes . They convert the collected analog voltage signals into digital signals, which are analyzed, processed, stored, displayed or printed by the internal microprocessor. This type of oscilloscope usually has program control and remote control capabilities, and can also transmit data to external devices such as computers for analysis and processing through the GPIO interface. With the continuous development of large-scale integrated circuits, thereal-time performance of powerful DSP digital signal processors is getting stronger and stronger. With its powerful digital signal processing capabilities, DSP provides a reliable and practical platform for the implementation of the data acquisition system of the digital oscilloscope, and improvesthe sampling rate, storage depth, waveform capture capability and other indicators of the digital storage oscilloscope.

The digital storage oscilloscope card 　　described in this article is a dual-channel digital storage oscilloscope based on DSP . The oscilloscope uses the TMS320F2812 chip from TI, which has high-speed digital signal processing capabilities and filtering functions, as well as real-time, large-capacity waveform storage, fast signal processing and other characteristics. And this digital storage oscilloscope has the advantages of portability, simple operation, high accuracy, and high sampling rate.

　　2. Overall design

　　The digital oscilloscope is mainly composed of front-end voltage stabilization processing circuit, AD conversion circuit, NIOS system integrated in FPGA chip, various control circuits and SDRAM, various keyboards and LCD interfaces, etc. The DSP chip used as the core of the back-end processing is TMS320F2812 from TI. It is a 32-bit fixed-point DSP chip with 128K*64-bit on-chip Flash memory, 18K*16-bit data/program memory and 4K*16-bit Boot Rom. The FPGA chip used as the front-end acquisition control processor is EP2C5Q208 from Altera. It is a low-cost FPGA chip from the Cyclone series with up to 119808 bits of internal RAM, 4608 logic units, and supports NIOSII and SOPC from Altera, which can meet the design requirements.

　　As shown in Figure 1, the measured signal first comes from channel 1 or channel 2. Since the amplitude of the analog signal received by the two channels is in an unstable state, it must be processed by the conditioning circuit into a voltage range that the A/D conversion circuit can receive, otherwise it will cause very serious consequences. The A/D conversion circuit can convert the conditioned analog signal into a digital signal after sampling, holding, quantization, encoding and other processes, and send it to the FPGA chip under the action of the SDRAM controller. Under the overall control of the NIOS built into the FPGA, the internal FIFO is used for buffering and corresponding data processing.

　　In this design, DSP is the core of the entire oscilloscope card data processing and display. It performs the main data processing and outputs the processing results and corresponding control signals. FPGA works under the control signal sent by DSP. DSP is a high-speed digital signal processor. The data processed by FPGA and stored in the buffer memory is sent to the original buffer in SDRAM under the control signal of DSP. After being processed by various algorithms such as DSP difference and filtering, it is sent to the display buffer of the oscilloscope card for waveform display on the LCD screen.

　　2.1 Design of front-end conditioning circuit and A/D sampling

　　Generally, the voltage amplitude allowed for input by A/D chips is fixed (-0.5v~+0.5v). The preprocessing circuit composed of various signal attenuation and amplification and voltage bias network is responsible for stabilizing the unstable analog signal received by the front end within the allowed input voltage range after attenuation. Generally speaking, the front-end preprocessing circuit consists of two parts. One is the attenuation network composed of relays and RC, which can avoid signal distortion and facilitate the reference adjustment of the digital storage oscilloscope card; the other is the resistor-capacitor matching network and drive amplifier circuit composed of two AD8008 op amps. AD8008 is a dual-channel , high-performance, current feedback amplifier with ultra-low distortion and noise characteristics, a bandwidth of 650MHz, and a wide power supply voltage range (5V~12V).

　　The core of data acquisition is the A/D conversion function. Although the DSP chip itself has the function of A/D conversion, in order to improve its working speed, this design uses two AD9288 chips to complete the analog-to-digital conversion. Under the control of the sampling clock, a 180-degree phase difference is formed to meet the 200MS/s sampling rate.

　　AD9288 is a dual-core 8-bit single-chip sampling analog-to-digital converter with built-in on-chip sample-and-hold circuit. It has the characteristics of low cost, low power consumption, small size and easy to use. AD9288 operates at a conversion rate of 100MSPS and has excellent dynamic performance over the entire operating range. The output of AD9288 is binary code, which can be directly stored after being sent to the FPGA storage module. Each channel can work independently, with a maximum analog bandwidth of 475MHz, allowing dual channels to work in parallel.

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　　The trigger circuit is an important functional circuit of the signal acquisition system. Its basic function is to provide a stable trigger phase point, which is used as the time reference zero point of the horizontal scanning time base, so that the waveform can be displayed stably on the display screen. This acquisition circuit design realizes a trigger pulse signal with a cycle related to the measured signal to control ADC data acquisition.

　　The core component of the trigger circuit is the high-speed level comparator. The AD96685 chip and LT1713 chip are used in this acquisition circuit. The trigger circuit is shown in Figure 3. The TrigLevel signal is the comparison level superimposed with the low-frequency component of the source signal. Ref is the reference potential, and the Trig Source signal is the triggered source signal. The trigger level can be adjusted by changing the level value of the Trig Level signal. After comparison and shaping by LT1713, a pair of ECL differential clocks TrigP and TrigNP are output, and then sent to the trigger in the FPGA after level conversion.

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　　2.3 Design of power supply circuit

　　The power supply of the digital storage oscilloscope card is mainly divided into three parts, one part is for the high-speed A/D converter, the second part is for the FPGA, and the third part is for the DSP chip. Considering factors such as cost and practicality, the more common adjustable power supply LM1117 is used to power the A/D converter and FPGA.

　　The rated supply voltage required by the A/D converter is +3.3V. The power of a single-chip A/D converter under normal working conditions is 689mV, so the current consumed is about 210mA. The rated supply current of LM1117 is 800mA, and using two chips can better meet the requirements. FPGA power supply is divided into core power supply and IO port power supply. The core power supply voltage is 1.2V, which is powered by LM1117; the IO port can be configured in various ways including 1.5V, 1.8V, 2.5V, 3.0V and 3.3V, and its power supply is also provided by LM1117. The negative voltage required by devices such as the operational amplifier and field effect tube of the oscilloscope card is provided by LM2991. LM2991 is an output adjustable low-dropout regulator with an output voltage adjustment range of -2V to -25V (output current is 1A).

　　DSP needs to work under a more stable voltage. The dual voltage output chip TPS70151 produced by TI is used in the design of the oscilloscope card. This chip can provide two different voltages at the same time, and the power-on sequence can be changed by manual control. As shown in Figure 4, the two inputs VIN1 and VIN2 are connected to VDD5, and VOUT1 and VOUT2 output 3.3V and 1.8V. SEQ can be used to control the power-on sequence. The grounding instruction is set to a low level, then VOUT1 outputs 3.3V first, and VOUT2 starts to have an output voltage until the output voltage of VOUT1 reaches about 2.7V. MR1 and MR2 are used to manually set input voltage 1 and input voltage 2, which can be used to control the output level of RESET. When the input level of any of the two pins is low, RESET outputs a low level. The other control terminals are connected to the DSP chip, so we can control the power supply voltage by writing a C language program in the DSP.

　　2.4 LCD Display Design

　　In this design, the LCD used is FY43-4827-65K, which has a high-resolution color TFT display screen of 480*272. It uses a 16-bit standard 8080 bus interface mode and supports 65536 colors to make images. It has an ultra-high 24MHz no-wait bus read and write speed, and a single-point read and write cycle of up to 42ns, without any waiting, and can interface with any high-speed system. It has a unique video memory update window setting function, and users can specify the read and write area at will.

　　Due to the high requirements for the buffer, the oscilloscope card needs to expand the system memory, so SDRAM is added as a display buffer to store temporary data and intermediate results.

　　The LCD uses ILI9320 as the controller. ILI9230 has a unified timing logic (as shown in Figure 5) and very rich instruction encoding, supporting MSP430, 51, DSP, FPGA and other series of CPUs. According to the different instruction encodings in the LCD controller and the data port definitions in the DSP, you can also design your own control instructions and programming methods for the LCD to achieve combined control of the display position, display content and color on the LCD screen.

　　As shown in Figure 6, DSP exchanges data with SDRAM through the data bus and sends the processed data to the display buffer. At the same time, DSP can also send instructions to ILI9230 through the control bus to make it read data from SDRAM and send it to LCD display, thus completing a display process.

　3. Conclusion

　　This paper adopts the solution of DSP and FPGA to design an embedded digital storage oscilloscope . In the absence of an operating system, waveform processing, display and keyboard control are realized, which improves the operating efficiency of the CPU. In this solution, FPGA is the core of the front-end circuit logic control and does some early data processing; while DSP is the core of the entire system in this design. The filtering, difference process, display and control functions of the oscilloscope are all completed on the DSP chip, and the real-time response speed of the digital storage oscilloscope is improved. Through actual testing and use, the oscilloscope has basically met the initial design requirements, and various performances have also reached the predetermined indicators.