DSP Performance Analysis of FPGAs

    FPGAs are gaining more and more attention in high-performance digital signal processing applications, such as wireless base stations. In these applications, FPGAs are often used to work in parallel with DSP processors. Having more choices is good, but it also means that system designers need a clear performance parameter map of FPGAs and high-end DSP signal processors. Unfortunately, commonly used parameter maps are unreliable in this case.

　　For example, since digital signal processing applications rely heavily on multiply-accumulate (MAC) operations, DSP processor vendors and FPGA vendors often use the maximum number of MACs per second as the easiest way to measure digital signal processor performance. But it is unfair to predict digital signal processing performance based solely on MAC throughput, and the same is true for FPGAs and DSPs. There are several reasons for this.

　　FPGA performance indices calculated using MAC always assume that the hardwired digital signal processing components are running at their highest clock rate. In practice, typical FPGA designs will use lower speeds. On the other hand, using hardwired principles is not the only way to implement MAC on an FPGA; MAC throughput can also be achieved by using programmable logic resources and distributed algorithms. In addition, not all signal processing algorithms are MAC-intensive. For example, Viterbi decoding, a key DSP algorithm in telecommunications applications, does not use a MAC system.

　　Another approach to evaluating signal processing performance is to use common DSP functions (such as FIR filters). However, this approach has its drawbacks. One problem is that each vendor typically implements these functions differently, perhaps using different data widths, different algorithms, or different execution parameters (such as delays). This means that conclusions drawn from different vendors are generally not comparable. In addition, small kernel functions are generally not valid FPGA benchmarks because the way a function is implemented in a complete FPGA application is often completely different from how you would implement the function in isolation. (Compared to processors, these small benchmarks are usually good at predicting overall DSP application performance.) In addition, benchmarks implemented by processor or FPGA vendors often lack independent verification, making it difficult for engineers to compare several devices.

　　Several years ago, BDTI recognized the growing need to establish independence, specifically, to compare FPGAs and processors in an apples-to-apples manner for digital signal processing applications. (See sidebar: What is BDTI?) To meet this need, BDTI developed a new application-oriented benchmark, the BDTI Communications Benchmark (OFDM)?, which is based on orthogonal frequency division multiplexing (OFDM) receivers.

　　BDTI recently used the BDTI Communications Benchmark (OFDM) to evaluate some new high-performance FPGAs and DSP processors. The full set of benchmark test results and analysis are now published in the BDTI report "DSP Implementation in FPGAs: Second Edition". Figure 1 shows the sample normalized, low-cost results for the Xilinx SX25 and a typical high-performance DSP processor.

　　As shown in this figure, BDTI's benchmark results provide a dramatic demonstration of the potential cost advantages of using FPGAs in high-performance DSP applications - based on this benchmark, the SX25 is more cost-effective than typical high-performance DSP processors by more than an order of magnitude.

　　Designers also need to understand how the chosen processing engine will affect their development flow, implementation effort, and system design. For this reason, a BDTI report explores the qualitative factors that influence the decision whether to use an FPGA, digital signal processing, or both, and provides guidance on how to make an informed choice. The report highlights key open issues that will affect the long-term success of FPGAs in high-end DSP applications, such as FPGA energy efficiency and the efficiency of new high-level synthesis tools for FPGAs.