Application reference of programmable logic devices

introduction

With the development of large-scale and ultra-large-scale programmable logic devices, logic devices are increasingly widely used in electronic circuit design with their low price, flexible design methods, and rich and complete functions. CPLD can be used to comprehensively integrate the functions of logic circuits, design the smallest unit according to needs, save system resources, and greatly reduce the functional modules and connections between modules on the circuit board. At the same time, with its flexible design and online upgrade method, the system can be modified and upgraded, which reduces the modification of the circuit board itself, improves the overall reliability of the system, saves the plate making cost, and shortens the design cycle.

However, there are still many details that need to be paid attention to when using programmable logic devices, especially for electronic circuit designers who are just beginning to use them for design. Only by grasping these details can they successfully carry out the design.

Application Basics

Before designing, you need to understand the logic device. Taking the MAX7000 series as an example, the device pin settings are shown in Figure 1. This is an example of applying CPLD devices to PCI interface logic, realizing the decoding of local control signals output by the PCI interface chip and the embedded design of some functional modules.

Excluding the pins required for the power supply part of the component, most of the remaining pins are I/O ports, which can be defined as the control pins required by the system. It is necessary to pay attention to several global signal control pins, such as GCLK, OE and other pins, which can be used to control the working timing of the entire logic device, and are generally used for the connection of global signals. It is also necessary to note that the four pins TDI, TMS, TDO, and TCK are program download pins related to online programming, and can also be used as general pins when necessary. The download line of ALTERA components can be purchased or made by yourself, and the information is relatively complete. To achieve online programming, it is necessary to pay attention to the PCB design of the CPLD component part that several download pins are not suspended, and must be designed with pull-up and pull-down. The circuit is shown in Figure 2. This point is easy to overlook, resulting in the download software being unable to discover the lower-level devices. The relevant instructions are in the document "In-System Programmability".

By installing the corresponding download line driver in the operating system, you can find the programmable control device in its graphical design software and perform online programming and debugging on it. [page]

Control logic design

The great advantage of CPLD is its flexibility. Combinatorial logic can be designed according to needs, which reduces the use of discrete components and improves the integration and reliability of the system. For general applications, MAX+plus editing software can be used. Its interface is simple and all functions are integrated in the menu, which can easily complete the whole process of design, synthesis, simulation and download. Figure 3 shows the PCI interface decoding circuit designed with the corresponding soft core of 74LS154, so as to realize 4-16 decoding inside CPLD. The pins used can be marked in the circuit diagram, and can be configured as needed to facilitate the wiring optimization of external PCB design.

Using ALTERA's hardware development language AHDL and general hardware description design languages ​​such as VHDL can realize independent development of soft cores, and at the same time can realize synchronous simulation to verify the logical correctness of the design. The following is an example of digital divider design.

SUBDESIGN NDivide

(

clk :INPUT;

clkoutD :OUTPUT;%Even frequency output%

BXCOUNTout[3..0] :OUTPUT;

COUNTAOUT[2..0] :OUTPUT;

)

VARIABLE

%Even frequency variable%

COUNTD[3..0] :DFF;% less than 16 divider, even

Digital divider %

clkRegD :DFF;

BEGIN

%Even frequency division part%

COUNTD[].clk=!(clk);

clkRegD.d=!clkRegD.q;

clkoutD=clkRegD.q;

IF (COUNTD[].q==1) THEN% According to the frequency division number, 2 is divided into n+1

Frequency, here is 4 division, when it is 2 division, clkRegD.clk=!clk%

COUNTD[].d=0;

ELSE

COUNTD[].d=COUNTD[].q+1;

END IF;

clkRegD.clk=COUNTD0.q;

END;[page]

The program simulation waveform is shown in Figure 4, which realizes the logic design and implementation of the four-frequency division circuit.

PCB circuit design

When using CPLD, you should also pay attention to the high-frequency pulses generated when the state of its output pin changes, which will bring severe tests to the next-level devices. Therefore, corresponding processing must be performed in PCB design to effectively suppress the extreme value of the pulse and ensure the steepness of the rising edge. Figure 5 is an output effect diagram of a pulse width modulation soft core. This module realizes pulse width modulation with an accuracy of 8 bits. The base frequency of the square wave signal is 4kHz, which is obtained by dividing the 33M PCI clock. The system only uses the simplest resistor-capacitor filter circuit to reduce the pulse value.

The figure shows the oscilloscope display under two conditions: direct output and filtered output. In figure a, no filtering measures are taken. It can be seen that there is a peak pulse of about 4V at the rising edge, which is 1V higher than the stable high-level 3V output. Figure b is the output after a simple resistor-capacitor filter circuit, and the peak of the rising edge pulse is obviously suppressed. This greatly improves the performance of the system.

Conclusion

The application of programmable logic devices can accelerate the development process. Functional simulation and verification in the environment provided by the device can timely discover design defects. However, the built-in simulator itself is not perfect, and more detailed verification is required after the circuit design is completed. The widespread application of CPLD gives electronic circuit designers more room to play and more flexible design methods, which greatly improves design efficiency.