FPGA technology high frequency fatigue testing machine controller

Introduction to FPGA

Field Programmable Gate Array (FPGA) is a general-purpose user-programmable device first developed by Xilinx in the United States in 1984. FPGA has both the high integration and versatility of gate array devices and the user-programmable flexibility of programmable logic devices.

FPGA consists of a programmable logic cell array, wiring resources and a programmable I/O cell array. An FPGA contains a wealth of logic gates, registers and I/O resources. One FPGA chip can implement a system that can be implemented by hundreds or even more standard digital integrated circuits.

FPGA has a flexible structure. Its logic units, programmable internal connections and I/O units can be programmed by users to realize any logic function and meet various design requirements. It has high speed, low power consumption and strong versatility, and is particularly suitable for the design of complex systems. FPGA can also be used to realize dynamic configuration, online system reconstruction (the function of the circuit can be changed as needed at different times of system operation, so that the system has a variety of space-related or time-related tasks), hardware softening, software hardening and other functions.

In view of the large control scale and complex functions of the high-frequency fatigue testing machine controller, during the development process, based on the traditional testing machine controller, we combined FPGA technology and microcomputer technology to comprehensively improve the performance of the controller system, thereby improving the working efficiency, control accuracy and electrical system reliability of the whole machine, and making it easy to operate and technologically advanced.

2 Controller structure and content

The overall structure of this control system, the lower computer is the core of the entire high-frequency fatigue testing machine controller. It is used to generate control signals and data for the control test machine, process feedback signals, and communicate data with the upper computer. The strength of its control function also directly affects the performance of the entire controller. The waveform generator in the figure is used to excite and maintain the vibration of the electromagnetic exciter. Here, the waveform generator should output a sine wave.

3 Technical route adopted by the system

On the basis of realizing technical parameters and functional requirements, the system adopts the following main technical routes in combination with current microcomputer, FPGA and other microelectronic technologies:

(1) The lower computer is the core of the system control. Since the control scale of this system is relatively complex, the control object has certain special features (such as high frequency, high load, etc.), and it involves controlling the motor, the traditional 8-bit computer is not used, but the 16-bit computer with relatively more powerful functions and faster speed, the 87C196 series, is considered.

(2) The exciter requires the input waveform to be a sine wave, and the test frequency range is 80 to 250 Hz. In addition, the system should also be able to perform a frequency sweep test. In the frequency sweep test, the system sweeps the frequency (coarse adjustment) with a step size of 1 Hz, and then performs fine adjustment (with a step size of 0.1 Hz) on the basis of the coarse adjustment to determine the resonance point of the system. It can be seen that the circuit module that can generate a waveform with an accuracy of 0.1 Hz is a very critical part of the entire system design and one of the design difficulties. This part cannot or is difficult to achieve through a single-chip microcomputer or other dedicated chips. The system uses FPGA as a waveform generator, as shown in the dotted box in Figure 1. The advantages of this are: high speed (generally the chip frequency is at least tens of megahertz, or even hundreds of megahertz) and can meet the above-mentioned accuracy requirements; it is implemented using digital circuits and has good anti-interference performance; other logic circuits can also be integrated into the chip, saving many discrete components and reducing the volume; the waveform can be changed as needed.

(3) DC speed regulation is achieved through voltage transformation, which is accomplished through a controlled rectifier using a thyristor. The microcontroller outputs a variable voltage to a phase-shift trigger, which in turn outputs a controllable conduction angle to the controlled rectifier to adjust the motor speed. This helps improve system reliability.

(4) Some important signals of the system are filtered by digital filters, which are implemented by FPGA. Compared with software filtering, this method is conducive to improving the filtering effect of the signal and greatly improving the filtering speed.

4. Part Module Design

The FPGA part can be divided into two modules, among which the sine wave generator module can be further divided into several small modules, as shown in Figure 2.

4.1 Latch Design

The latch is used to latch and stabilize the frequency data sent by the microcontroller in the FPGA, and can be constructed using the latch resources on the chip (or using a trigger). [page]

4.2 Design of the operator

The operator is used to convert the frequency data into the timing data between the sine wave points. The operator can actually be converted into a divider. The divider is described as follows:

—VECTOR(WIDTH— R-1 DOWNTO 0));

END COMPONENT;

The above description actually calls a component in Altera's parameterized module library (LPM). After describing the component, you only need to use Generic map and port map statements to map the component in the program. It should be noted that the port signal remainder is the result of the modulo operation of numerator and denominator, so remainder should be compared with denominator/2, and the actual result should be determined based on the comparison to determine whether to add 1 or not.

4.3 Timer Design

The timer is set according to the timing data sent by the operator. It can be realized by counting the reference clock. When the timing time is reached, the waveform output is triggered.

The design uses two counting modules to count simultaneously, one module counts the rising edge of the clock, and the other module counts the falling edge of the clock. This is equivalent to doubling the system clock frequency and making full use of system resources.

4.4 Waveform Output

The waveform output is the sine value at that time when the timer is triggered to meet the timing requirements. The trigger output of multiple points forms a sine wave.

In order to save chip resources, this part of the function of finding the sine value at a certain time does not use the construction operator to calculate the sine value, but uses a lookup table structure. For example, Xilinx's FPGA chip can use CLB blocks to configure RAM or directly use Logiblox to generate it. There are also Altera's Flex10k series that use a lookup table structure (LUT) to build on-chip ROM or RAM. After creating a RAM or ROM block in the project file, the sine value of each moment (expressed in ASCII characters) can be written into the MIF file (initialization file) and stored in the RAM or ROM block. After the timer is triggered, the address of the time is generated, and the sine value of the time can be output by querying the RAM or ROM block.

5. Specific implementation of the chip

The FPGA of this system uses Altera's Flex10k series chips. The chip uses the development software Max+plusII to describe and input each module (the dotted box part in Figure 1) in VHDL language. The software automatically compiles, synthesizes, lays out and routes, generates data files for programming, and loads them into the configuration storage unit of the FPGA. There are many modes for configuring the FPGA chip. Since there is a single-chip microcomputer in this system, the serial slave mode is used, which saves the use of an EPROM to store programming data. When the system is powered on, the single-chip microcomputer automatically sends the configuration data stored in it to the internal storage unit of the FPGA.

This technology is basically used in circuits.