Altera Releases Single-Chip FPGA High-Definition Internet Protocol Surveillance Camera

Altera Corporation today announced the industry's first single-chip FPGA high-definition (HD) Internet Protocol (IP) surveillance camera reference design, further providing expanded FPGA solutions for the surveillance market. This unique solution uses Altera's low-cost Cyclone III or Cyclone IV FPGA and intellectual property from Eyelytics and Apical to support AltaSens' 1080p60 A3372E3-4T and Aptina's 720p60 MT9M033 HD wide dynamic range (WDR) C MOS image sensors . Compared to existing architectures using traditional digital signal processors and ASSPs, this fully integrated solution helps surveillance equipment manufacturers reduce board area, power consumption, increase flexibility and shorten development time.

Traditional digital signal processors and ASSPs are not equipped to handle the wideband data from 1080p and 720p WDR CMOS sensors (e.g., a full HD raster is 2200x1125 pixels x 16 + bits per pixel x 60 frames per second, which gives a bandwidth of >2 Gbps). Altera Cyclone family FPGAs have the bandwidth and processing power required to handle the large amounts of data generated by today’s HD WDR CMOS image sensors . In previous designs, HD WDR camera systems required an FPGA to perform the “front end” data processing, while a digital signal processor or ASSP handled the “back end” video encoding . Now, all of these chips can be replaced with an Altera? FPGA.

Altera HD Surveillance IP Camera Features of the reference design include:

Apical ISP best-in-class WDR processing “iridix” and advanced temporal and spatial noise suppression capabilities.

Apical "chessboard demosaicing" core for use in Altasens A3372E3-4T WDR mode.

"3A" functions, such as auto-exposure and auto-white balance, are implemented on the Altera Nios? II embedded soft-core processor.

Eyelytics' H.264 video encoder is capable of encoding Main Profile 720 progressive lines at 30 frames per second, or 1080 progressive lines at 15 frames per second.

Altera's Triple-Speed ​​Ethernet MAC intellectual property core.

By eliminating the need for a digital signal processor or ASSP, integrating all of these functions into an Altera FPGA allows designers to reduce board area, thereby reducing costs and saving power. Altera's single-chip solution consumes more than 50% less power than previous designs.

A full set of intellectual property is bundled in this reference design to help designers quickly start camera development, reducing development time by nearly a year. All the camera designer needs to do is customize the FPGA with their specific functions, for example, adding their own software for motion detection, pan, tilt and zoom control, etc.

"Much like the video display industry, our customers in the surveillance market expect high-quality video images," said Michael Samuelian, director of Altera's industrial and automotive business. "Altera has implemented a complete single-chip solution that not only addresses the trend from standard definition to high definition and from standard CMOS sensors to WDR CMOS sensors, but also helps surveillance camera designers to cost-effectively transmit high-resolution images over Internet Protocol networks, further advancing video surveillance technology."