Design of a driver interface circuit based on FPGA

introduction

In many applications of automatic control, it is necessary to sample and analyze the signal in real time, and then the DSP will perform the operation and control. AD chip is the most commonly used chip in sampling. This article mainly introduces the AD7862 chip of ADI Company, and designs a driving interface circuit for it. Since AD7862 cannot work automatically, it needs to be provided with relevant driving signals to trigger it to convert. This article uses FPGA chip to make an interface driving circuit for it, and introduces the design of the driving circuit program in detail. The designed circuit provides a very good driving effect for AD7862, and can make it work stably in actual application.

1. AD7862 chip introduction

AD7862 is a 12-bit high-speed, low-power converter produced by ADI Corporation of the United States, powered by a single 5V power supply. There are 4 analog input terminals, divided into two channels (A & B), which are selected by input terminal A0. Each channel has two input terminals (VA1 & VA2 or VB1 & VB2). The acceptable input range of analog signals is plus or minus 10V. However, the overvoltage protection of the analog signal input terminal allows the input voltage to reach plus or minus 17V. The principle block diagram is shown in Figure 1.

Figure 1. AD7862 block diagram.

The AD7862 chip has the following features:

(1) For each channel, it takes 3.6 s from the start of conversion to the completion of conversion.

(2) The chip is powered by a single 5 V power supply, with low power consumption, typically 60 mW when working. It has an automatic sleep mode, which automatically enters sleep mode after a conversion is completed to save power. It automatically wakes up when the next conversion cycle comes.

(3) Provides a high-speed parallel interface, making it easy to connect to microprocessors, microcontrollers and digital signal processors.

(4) The AD7862 series has three versions for three different input ranges. The AD7862-10 is for the standard industrial input range of +/-10V; the AD7862-3 is mainly for the normal signal input range of +/-2.5V.

The AD7862-2 is used for unipolar 0 to 2.5 V input range. For the AD7862-10 and AD7862-3, the 12-bit conversion output is two's complement, and for the AD7862-2, the output is 12-bit original code.

2. Interface circuit program design

In this design, AD7862??10 is used, and high-speed conversion mode is adopted. The typical conversion timing is shown in Figure 2.

Figure 2 High-speed conversion mode timing diagram.

The requirements for the corresponding time parameters in FIG. 2 are shown in Table 1 below.

Table 1 High-speed sampling mode timing parameters.

From the timing diagram in Figure 2, we can see that AD7862 starts conversion by inputting pulse signal CONVST. At the falling edge of CONVST signal, both track/hold on the chip are set to hold state at the same time, and two channels start to convert. The conversion clock is provided by the built-in crystal oscillator. BUSY signal indicates the end of conversion, and the conversion results of two channels can be read out at the same time. The value of A0 determines whether the first read value is VA1 or VB1, and the second read value is VA2 or VB2. When CS signal and RD signal are low, data is read from 12-bit parallel data line. In high-speed conversion mode, the conversion time of AD7862 is 3.6 us, and the track/hold collection time is 0.3 us. In order to ensure the best conversion effect, the reading operation cannot be performed during the conversion and 300 ns before the next conversion starts.

The above timing diagram corresponds to reading VA1 and VA2 first, then reading VB1 and VB2, and the corresponding signal A0 is first set to a low level and then pulled to a high level. In the process of designing the driving circuit, it is necessary to ensure that the designed timing meets the requirements of the above timing parameters, otherwise inaccurate sampling and errors may occur.

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