Research and implementation of DDS FM signal based on FPGA

1 Introduction
　　Direct Digital Synthesizer (DDS) technology has fast frequency switching speed, easy to improve frequency resolution, low hardware requirements, programmable full digitalization to facilitate single-chip integration, which is beneficial to reducing costs, improving reliability and facilitating production. Etc. At present, major chip manufacturers have successively launched high-performance and multi-functional DDS chips produced using advanced CMOS technology. The dedicated DDS chips use a specific process, the internal digital signal jitter is very small, and the quality of the output signal is high. However, in some cases, because the control method of the dedicated DDS chip is fixed, there is a big gap with the system requirements in terms of working mode, frequency control, etc. At this time, if you use high-performance FPGA devices to design a DDS that meets your needs, The circuit is a good solution. Its reconfigurable structure can easily realize various complex modulation functions and has good practicality and flexibility.

2DDS FM signal generator block diagram design

3DDS modulated signal generator FPGA circuit design

Figure 2
　　shows the FPGA circuit design diagram of the core unit of the DDS modulated signal generator. The design scheme uses ALTERA's Cyclone series EP1C6T144C6 chip, the adder is 12 bits, the modulation signal waveform memory is 4096×12BIT, the carrier signal waveform memory is 4096×12BIT, and the system clock is 80MHz; design performance parameters: the carrier frequency can reach 10MHz (To ensure that the waveform is not distorted, at least 8 points are taken in one cycle), the modulation frequency range is 0~100K, and the FM depth is 0~10. The external circuit inputs include modulation signal frequency control word Kh[11..0], carrier signal frequency control word Kc[11..0], frequency offset control word Kx[11..0], modulation signal system clock TZCLK, carrier signal System clock ZBCLK. Kh[11..0] outputs the accumulated phase ADDA[11..0] through accumulator A as the address of the modulation signal lookup table, and the waveform data Qa[11..0] and Kx[11..0] and Kc[11 ..0] After numerical conversion, the frequency modulation control word K[11..0] is output. K[11..0] outputs the accumulated phase ADDB[11..0] through accumulator B as the address of the FM signal lookup table. The waveform data Qb[11..0] is converted by an external DAC and low-pass filtered to obtain the FM signal waveform. . Among them, the DFF buffer connected after the two accumulators helps eliminate the impact of glitches and further ensures the stability and reliability of the system.

4 Simulation and Experiment

　　Assume that the carrier system time scale frequency is 1MHz, the modulation signal system time scale frequency is 100KHz, the phase accumulator has 8 bits, and both the address and data bits of the two waveform memories are 8 bits. Use QUERTUS Ⅱ 3.0 to simulate, see Figure 3; use matlab 6.5 to simulate, see Figure 4; use the AEDK-EDA experimental box to download (the FPAG chip is EPF10K10TC144-4), and the D/A conversion and unipolar output circuit are implemented with the ispPAC20 chip. Observe the waveform through Tektronix TDS3054B oscilloscope, and the results are shown in Figure 5. Among them, the number of D/A digits is 8, the measurement range is -4-+4V, and the peak value of the carrier signal is 1.414V. From the frequency modulation and demodulation waveform data in Figure 4 and Figure 5, the carrier frequency is 14.2kHz, and the error is -3.06% ; The modulation frequency deviation is 480Hz, the error is -1.69%; the modulation degree is M=10.21%, the error is 2.1%, the modulation frequency is 4.82kHz, the error is -1.23%. It can be seen from the experimental results that the design theory and design circuit provided in this article are not only correct and feasible, but also have good performance parameters. The consistency of all design, simulation and experimental results provides an excellent design solution for the FPGA implementation of the DDS FM signal generator.
 

　　　　　　　　　　　Figure 3 DDS FM wave simulation diagram (QUERTUS II)

Figure 4 DDS FM wave simulation diagram (matlab) Figure 5 DDS FM wave experimental results diagram

5 Summary

　　Using FPGA to implement a DDS frequency modulation signal circuit is more flexible than using a dedicated DDS chip. As long as the data and control parameters in the ROM in the FPGA are changed, DDS can generate arbitrary modulation waveforms with high resolution and considerable flexibility. In contrast, the function of DDS depends entirely on the design requirements, which can be complex or simple, and the FPGA chip also supports on-site upgrade of the system. In addition, embedding DDS design into a system composed of FPGA chips will not increase the system cost much, while the price of purchasing dedicated chips is many times that of the former. Therefore, using FPGA to design a DDS system is very cost-effective.

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