Design of ESD protection structure for CMOS circuit

1 Introduction

Electrostatic discharge can have destructive consequences on electronic devices and is one of the main causes of integrated circuit failure. With the continuous development of integrated circuit technology, the characteristic size of CMOS circuits has been continuously reduced, the gate oxide thickness of the tube has become thinner and thinner, the area of ​​the chip has become larger and larger, and the current and voltage that MOS tubes can withstand have become smaller and smaller, while the peripheral use environment has not changed. Therefore, in order to further optimize the circuit's anti-ESD performance, how to make the effective area of ​​the entire chip as small as possible, the ESD performance reliability meets the requirements, and no additional process steps are required has become the main consideration for IC designers.

2 ESD Protection Principle

The design purpose of ESD protection circuit is to prevent the working circuit from becoming the discharge path of ESD and being damaged, and to ensure that when ESD occurs between any two chip pins, there is a suitable low-resistance bypass to introduce the ESD current into the power line. This low-resistance bypass must not only be able to absorb the ESD current, but also be able to clamp the voltage of the working circuit to prevent the working circuit from being damaged due to voltage overload. When the circuit is working normally, the anti-static structure does not work, which requires the ESD protection circuit to have good working stability and be able to respond quickly when ESD occurs. While protecting the circuit, the anti-static structure itself cannot be damaged, and the negative effects of the anti-static structure (such as input delay) must be within an acceptable range, and prevent the anti-static structure from latching.

3 Design of ESD protection structure for CMOS circuits

Most of the ESD current comes from outside the circuit, so the ESD protection circuit is generally designed next to the PAD and inside the I/O circuit. A typical I/O circuit consists of two parts: an output driver and an input receiver. ESD is introduced into the chip through the PAD, so all devices in the I/O that are directly connected to the PAD need to establish an ESD low-resistance bypass parallel to it, introduce the ESD current into the voltage line, and then distribute it to each pin of the chip from the voltage line to reduce the impact of ESD. Specifically for the I/O circuit, that is, the output driver and input receiver connected to the PAD, it must be ensured that when ESD occurs, a low-resistance path parallel to the protection circuit is formed to bypass the ESD current and immediately and effectively clamp the protection circuit voltage. When these two parts work normally, the normal operation of the circuit is not affected.

Commonly used ESD protection devices include resistors, diodes, bipolar transistors, MOS tubes, thyristors, etc. Since MOS tubes are compatible with CMOS processes, they are often used to construct protection circuits.

The NMOS tube under CMOS process conditions has a lateral parasitic n-p-n (source-p-type substrate-drain) transistor, which can absorb a large amount of current when turned on. This phenomenon can be used to design a protection circuit with a higher ESD withstand voltage value in a smaller area. The most typical device structure is the gate grounded NMOS (GGNMOS, Gate Grounded NMOS).

Under normal working conditions, the NMOS lateral transistor will not conduct. When ESD occurs, the depletion region of the drain and substrate will avalanche, accompanied by the generation of electron-hole pairs. A portion of the generated holes are absorbed by the source, and the rest flow through the substrate. Due to the existence of the substrate resistance Rsub, the substrate voltage is increased. When the PN junction between the substrate and the source is forward biased, electrons are emitted from the source into the substrate. These electrons are accelerated under the action of the electric field between the source and the drain, resulting in collision ionization of electrons and holes, thereby forming more electron-hole pairs, causing the current flowing through the n-p-n transistor to increase continuously, and eventually causing the NMOS transistor to undergo secondary breakdown. At this time, the breakdown is no longer reversible, and the NMOS tube is damaged.

In order to further reduce the voltage across the NMOS on the output driver during ESD, a resistor can be added between the ESD protection device and the GGNMOS. This resistor cannot affect the working signal, so it cannot be too large. Polysilicon (poly) resistors are usually used when drawing the layout.

Only using the first level of ESD protection, the tube inside the circuit may still be broken down when the ESD current is large. When the GGNMOS is turned on, due to the large ESD current, the resistance on the substrate and the metal connection cannot be ignored. At this time, the GGNMOS cannot clamp the input receiving end gate voltage, because it is the IR voltage drop between the GGNMOS and the input receiving end substrate that makes the voltage of the gate silicon oxide layer of the input receiving end reach the breakdown voltage. To avoid this situation, a small GGNMOS can be added near the input receiving end for second level ESD protection, which is used to clamp the input receiving end gate voltage, as shown in Figure 1.

Figure 1 Common ESD protection structures and equivalent circuits.

When drawing the layout, it is important to place the secondary ESD protection circuit close to the input receiving end to reduce the resistance of the substrate and its connection between the input receiving end and the secondary ESD protection circuit. In order to draw a large-sized NMOS tube in a smaller area, it is often drawn as a finger shape in the layout. When drawing the layout, the I/O ESD design rules should be strictly followed.

If the PAD is used only as output, the protection resistor and the NMOS with short gate to ground are not needed. The large-sized PMOS and NMOS devices in the output stage can be used as ESD protection devices. Generally, the output stage has double protection rings to prevent latch-up.

When designing the ESD structure of the full chip, pay attention to the following principles:

(1) Make the peripheral VDD and VSS lines as wide as possible to reduce the resistance on the lines; (2) Design a voltage clamping structure between VDD and VSS that can provide a direct low-impedance current discharge channel between VDD and VSS when ESD occurs. For circuits with a larger area, it is best to place such a structure around the chip. If possible, placing multiple VDD and VSS PADs on the periphery of the chip can also enhance the overall circuit's ESD resistance. (3) The power and ground routing of the peripheral protection structure should be separated from the internal routing as much as possible, and the peripheral ESD protection structure should be designed as uniformly as possible to avoid ESD weak links in the layout design. (4) The design of the ESD protection structure should balance the ESD performance of the circuit, the chip area, and the impact of the protection structure on the circuit characteristics such as input signal integrity, circuit speed, and output drive capability. The tolerance of the process should also be considered to optimize the circuit design. (5) In some actual designed circuits, there is sometimes no direct VDD-VSS voltage clamping protection structure. At this time, the voltage clamping and ESD current discharge between VDD-VSS mainly utilize the contact space between the well and the substrate of the entire chip circuit. Therefore, the contact between the well and the substrate should be increased as much as possible in the peripheral circuit, and the spacing between N+P+ should be consistent. If there is space, it is best to add a VDD - VSS voltage clamp protection structure next to and around the VDD and VSS PADs. This not only enhances the ESD resistance in the VDD - VSS mode, but also enhances the ESD resistance in the I/O - I/O mode.

Generally speaking, as long as the above principles are followed and the chip area is compromised, the ESD voltage resistance of general sub-micron CMOS circuits can reach more than 2500V, which can meet the ESD reliability requirements of commercial civilian circuit design.

For the ESD structure design of deep submicron ultra-large-scale CMOS IC, conventional ESD protection structures are usually no longer used. Usually, most foundry production lines with deep submicron processes have their own peripheral standard ESD structures and strict standard ESD structure design rules. Designers only need to call their structures, which allows chip designers to focus more on the design of the circuit's functions, performance, etc.

4 Conclusion

ESD protection design is becoming more and more difficult with the improvement of CMOS process level. ESD protection is no longer just an ESD protection design problem of input pins or output pins, but an electrostatic protection problem of the entire chip.

A corresponding ESD protection circuit needs to be established in each I/O circuit in the chip. In addition, the entire chip must be considered as a whole. Using a whole-chip protection structure is a good choice and can also save the area of ​​ESD components on the I/O PAD.