CMOS Pulse Frequency Doubler

The pulse frequency multiplier is composed of CMOS gate circuits. Its output pulse frequency is twice the input pulse frequency. Its circuit is shown in Figure 1. The circuit consists of two RC differential circuits, an inverter and a 2-input NAND gate. The waveforms corresponding to each point are shown in Figure 2.

Working principle: The signal pulse is added from the input terminal in, and the pulse cycle time is T. When the pulse jumps positively through the gate "1" inverter, it becomes a negative jump at the output terminal a, and then passes through the differential network composed of R2 and C2 to generate a negative differential pulse, which is added to one input terminal of the "2" NAND gate, and the output terminal of the NAND gate changes from a low level to a high level. Then, +EC charges the capacitor C2 through R2, and the potential on C2 gradually rises until it equals the conversion voltage value of the NAND gate. The output terminal Out changes from a high level to a low level, forming a pulse output. The output pulse width is determined by the R2C2 time constant and the conversion voltage value of the NAND gate. When VTR (2) = Ec / 2, the output monostable pulse width tu = 0.69R2C2, when the falling edge of the input pulse arrives, the differential network composed of R1 and C1 generates a negative differential pulse, which is added to one of the input terminals of the "2" NAND gate, forming the second output pulse at the output terminal. That is, the circuit forms a pulse output at the output end for each transient edge of the input pulse, realizing the frequency doubling of the input pulse. It should be noted that if the circuit parameters are not intentionally adjusted, the duty cycle of the output pulse is not 50%, that is, the duty cycle is different due to the different relationship between the input pulse width and the RC time constant.