1 System Hardware Design
In the design of the ozone generator power supply, the commutation voltage drop generated by the thyristor SCR during three-phase rectification will have a serious impact on the output voltage average value and voltage waveform. Therefore, in the design of the main circuit of the power supply, a high-power diode rectification is used to replace the SCR rectification, so that the voltage pulsation output by the rectification circuit is very small, thereby improving the stability and efficiency of the power supply.
Since the rectifier part of the power supply uses uncontrollable diodes for rectification, the output voltage cannot be adjusted through the rectifier part. Therefore, the output voltage and frequency of the power supply can only be adjusted through the inverter part, that is, by controlling the duty cycle and frequency of the inverter trigger pulse, the output voltage and frequency of the power supply can be adjusted to meet the design requirements. The following focuses on how to adjust the duty cycle, frequency and soft start time.
1.1 Duty cycle adjustment unit
Figure 1 is a duty cycle adjustment circuit. This circuit uses the voltage signal output by the regulator as the input signal of the voltage controlled oscillator VCO (Voltage CON trolled Oscillator). This signal is a DC voltage signal that varies between 0 and 5 V, namely the INPUT signal. Since the VCO is a current controlled oscillator, the charging current of the timing capacitor C1 is proportional to the control voltage input from pin 9, so that the oscillation frequency of the VCO is proportional to the control voltage. When the VCO control voltage is 0 V, its output frequency is the lowest; when the input control voltage is equal to the power supply voltage VDD, the output frequency increases linearly to the highest output frequency. The range of the VCO oscillation frequency is determined by R1, R2 and C1. The VCO oscillation frequency is directly output from pin 4 of CD4046 to the CPLD processing unit. The CPLD controls the width of the inverter trigger pulse by counting the pulse signal to adjust the duty cycle of the trigger pulse.
1.2 Soft start time adjustment unit
Figure 2 is a soft start time adjustment circuit. This circuit unit uses the regulator output signal as the input signal of the voltage comparator LM339 . This signal is a DC voltage signal (i.e., INPUT signal) that varies between 0 and 5 V. According to the design requirements, the voltage given to pin 6 of LM339 is 1 V. When the voltage of the INPUT signal is greater than 1 V, pin 1 of LM339 outputs a high level as a start signal to the CPLD through a pull-up resistor . The output of the comparator is controlled by adjusting the external dial switch inside the CPLD, thereby controlling the soft start time .
1.3 Frequency Adjustment Unit
Figure 3 is a frequency adjustment circuit. By adjusting the CD4046 external potentiometer POT11, the frequency of the VCO output pulse is controlled. According to the design requirements, the circuit will output a pulse signal PLS with a range of 1 to 6 kHz, and use this signal as the input signal of the CPLD. Through the counting delay and duty cycle design requirements inside the CPLD, an inverter trigger signal with a frequency between 400 and 3,000 Hz that meets the duty cycle requirements is finally output, and the frequency of the signal can be adjusted through POT11.
2 System Software Design
The system software design is designed according to the system functional requirements. The software program design based on EPM7128 is divided into: output pulse duty cycle adjustment, frequency adjustment, soft start time adjustment and overvoltage and overcurrent alarm. The development system uses VHDL language for modular programming, which can improve the portability of the program, shorten the development cycle, and reduce the development cost. It is also easy to maintain the system software and improve reliability. Figure 4 is the output of the two-way PWM pulse simulation waveform, where GCLK is a reference clock source, CLKl and CLK2 are the frequency adjustment and duty cycle adjustment signals converted by VCO, and SET and SOFT are two external 4-bit duty cycle adjustment and soft start adjustment switches.
3 Conclusion
The software and hardware design of the ozone power control system based on CPLD is introduced . The application of digital circuits in the power control system enhances the reliability of the system and improves its functions. The control system can adjust the duty cycle of the output pulse and control the soft start time by adjusting the two external dial switches, making the power control more convenient and flexible. Through debugging on the industrial site, the control system can fully meet the control of the medium frequency ozone power supply, and has the advantages of strong anti-interference ability and good stability, and has a wide range of application prospects.
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