Design of Phase-locked and Protective Circuit for Photovoltaic Inverter Based on CPLD

In the inverter circuit of the photovoltaic grid-connected system, phase locking of the grid voltage is a key technology. Since the power system will generate large electromagnetic interference when working, its simple phase locking method is easily interfered and lost, resulting in the system being unable to operate normally. In this case, the design adopts a method of performing zero-crossing detection on the grid voltage and then sending the signal to the CPLD, and then the CPLD implements digital phase locking of the grid voltage, which can effectively prevent the phase from jittering or losing lock due to interference, and ensure the normal operation of the system. In addition, this system also uses CPLD to monitor the PWM wave control signal generated by DSP and various parameters during system operation. Once an abnormality is found, the system will be shut down immediately and the DSP will be notified of the abnormality, thereby realizing hardware protection of the system.

1 Overall structure of the system

The design method introduced in this article is part of the inverter of a 5 kW photovoltaic grid-connected power generation system. The photovoltaic grid-connected inverter can achieve maximum power tracking and grid-connected output of a solar cell array with a rated power of 5 kW. The system structure diagram of the inverter is shown in Figure 1.

This control system uses TI DSP2812 as the main control chip and Xilinx CPLD XC9572XL as the digital phase-locking and protection circuit. XC9572XL is a CPLD with a core voltage of 3.3 V. It consists of four 54V18 functional modules and can provide 1600 available gates with a delay of 5 ns.

2 Design and implementation of digital phase-locked circuit

The system structure diagram of the digital phase-locked circuit is shown in Figure 2. The circuit consists of a digital phase detector, a digital filter and a digitally controlled oscillator.

If the digital filter in the digital phase-locked circuit shown in Figure 2 is regarded as a frequency divider, its frequency division ratio is Mfc/K, and the output frequency at this time is:

f''=K''△φMfc/K

Among them, △φ is the phase difference between the input signal V1 and the output signal V2; fc is the center frequency of the loop. Then, the output frequency of the digital controlled oscillator is:

f2=f1+K''△φMfc(kN)

Since the locking limit range is K''△φ=±1, the capture band of the loop can be obtained:

△fmax=f2max-f1=Mfc(kN)

Thus, when the loop is locked, f2=f1 and the system steady-state phase error is:

△φ(∞)=NK(f2-f1)/(k''Mfc)

It can be seen that as long as the K value is reasonably selected, the phase of the output signal V2 can better track the phase of the input V1, thereby achieving the purpose of locking. If the K value is too large, the loop capture band will become smaller, which will lead to a longer capture time; and if K is too small, frequent carry and borrow pulses may occur, causing the phase to jitter.

According to the principle block diagram of the digital phase-locked loop given in Figure 2, the system can be designed using VHDL language. The digital filter is composed of a K-modulus counter, and the digitally controlled oscillator includes a pulse addition and subtraction control circuit and an N divider.

2.1 Digital Phase Detector

The digital phase detector can usually be an edge-controlled phase detector, an XOR gate phase detector, an XNOR gate phase detector or a phase detector composed of a JK trigger. This digital phase detector is a phase comparison device, which mainly generates an error signal Vd by comparing the phase of the input signal V1 (phase φ1) with the output signal V2 (phase φ2), and its phase difference is △φ=φ1-φ2. When △φ=φe (half the input signal pulse width), its phase detector output is a square wave, which belongs to the phase lock stage. In this case, as long as the K value of the reversible counter is large enough, its output end will not generate a carry pulse or a borrow pulse. When the loop is not locked, if △φ<φe, the duty cycle of its output pulse is less than 50%; and when △φ>φe, its duty cycle is greater than 50%, and the output voltage Vd will be added to the UPDN input of the K-module reversible counter.

2.2 Digital Filter

The counter can be designed as a 17-bit programmable (variable modulus) reversible counter with a counting range of 23 to 217, which can be controlled by an external setting DCBA. Its input frequency fk = Mfc. When the phase detector output Vd is high, the K modulus counter counts down, and when the count reaches "0", it outputs a borrow pulse DN; when the phase detector output Vd is low, the K counter counts up, and when the count reaches a certain set value "DCBA", it outputs a carry pulse UP. UP and DN can be used as the "add" and "subtract" pulse control signals of the pulse add/subtract circuit.

2.3 Digitally controlled oscillator

This circuit is composed of D flip-flop, JK flip-flop, AND gate, OR gate and other circuits. When the UP output terminal of the digital filter outputs a carry pulse, the system inserts a pulse signal at the output terminal fout of the pulse addition/subtraction circuit after the falling edge of INC arrives, that is, the phase is advanced by half a cycle; conversely, when the DN terminal of the digital filter outputs a borrow pulse, after the falling edge of DN arrives, the system will deduct a pulse signal from the output sequence of the pulse addition/subtraction circuit, that is, the phase is delayed by half a cycle, and this process occurs continuously. In this way, after the output of the pulse addition and subtraction circuit is divided by the N divider module (ncount), the phase of the output signal can be adjusted and controlled, and finally locked. When the loop is locked, there will be a certain phase error between the output and input signals.

3 Design and implementation of protection circuit

The protection circuit in this system is mainly composed of a PWM waveform monitoring module and a system parameter monitoring module. The protection circuit structure is shown in Figure 3.

The pulse width abnormality detection module in Figure 3 consists of three 9-bit enable counters. The three PWM signals output by the DSP are respectively used as the enable signal input of the counter. When the control signal is valid, the counter starts counting. The upper limit of the counter is 400, that is, 200μs. When the effective width of the control signal is less than 200μs (the control cycle of the DSP in this system is 55μs), it is considered that the PWM wave is normal and the system will directly output the control signal; if it is greater than 200μs, it is considered that the PWM wave is abnormal. At this time, the system will immediately cut off the effective output of the PWM wave and shut down. The abnormal interrupt signal and abnormal status code information are reported to the DSP. The common conduction module can be used to monitor the inverter system, thereby controlling the two symmetrical SPWM wave signals at the high and low ends of the half-bridge to ensure that the two signal outputs will not be in the common conduction state. In addition, the alarm signals such as system overvoltage, overcurrent and temperature abnormality generated by the analog comparator will be sent to the PWM wave processing module after digital filtering. In this way, when the system is abnormal, the CPLD can implement the hardware shutdown protection action.

Figure 4 shows the top-level diagram of the protection circuit. Figure 5 shows the simulation waveform of the protection circuit.

4 Conclusion

This paper introduces the design and implementation method of the phase-locked and protection circuit of the photovoltaic grid-connected inverter based on CPLD. The circuit has been successfully used in the project team's 5 kW photovoltaic grid-connected inverter. Actual use has proved that the circuit can provide reliable protection for the long-term stable operation of the system.