Design of Elevator Control System Based on FPGA

Abstract: This paper introduces the design of a four-story elevator control system based on FPGA. The system uses Altera's CycloneⅡ series FPGA chip EP2C5T144 as the main control chip, and uses Verilog-HDL programming description to realize intelligent control of the elevator. After simulation verification, the required functions are completed. The design adopts modular programming, and the upgrade can realize any multi-story elevator system, which has strong adaptability and practicality.
Keywords: elevator control; FPGA; Verilog; control module

0 Introduction
With the development of society, the use of elevators is becoming more and more common, and the requirements for elevator functions are constantly increasing, and the corresponding control methods are also constantly changing. The microcomputer control of elevators mainly includes: PLC control, single-board computer control, single-chip microcomputer control, single microcomputer control, multi-microcomputer control and artificial intelligence control. With the development of application-specific integrated circuit ASIC design technology and EDA technology, the widespread use of programmable logic devices has brought revolutionary changes to digital system design, changing the shortcomings of traditional circuit design, such as the use of many chips, complex circuits, difficulty in finding problems, and difficulty in function expansion. This design uses FPGA devices as the main control chip and Verilog-HDL language to design a four-story single passenger box elevator control system. The design adopts modular design, which is easy to modify and upgrade. It can be slightly improved to realize multi-story elevator control.

1 Overall design of elevator control system
1.1 Design tasks and requirements
Design a four-story elevator control system with the following requirements:
(1) Internal signals of each floor elevator: request buttons for each floor, door opening and closing request buttons, floor display, and elevator operation status display. External signals: up and down request buttons, floor display, and elevator operation status display.
(2) Able to store request signals. During the elevator ascent (descent) process, according to the elevator operation status, first respond to each request in direction priority and cyclic order.
(3) After reaching the requested floor, the indicator light of the floor lights up, the elevator door automatically opens, and the door opening indicator light lights up. After the delay waiting time, the elevator door automatically closes (the door opening indicator light goes out), and the elevator continues to run. When the elevator is idle, it stops at the 0th floor.
(4) It has an overload alarm function.
1.2 Hardware structure of the elevator control system
The hardware structure of the elevator control system is shown in Figure 1.

As shown in Figure 1, the system is mainly composed of FPGA controller, input signal modules, and output drive modules. The input signals of the FPGA control module include: elevator internal and external request signals, floor arrival signals, restart overload alarm signals, etc.; its output signals drive the display circuit, elevator door switch circuit, motor drive circuit, and other alarm circuits. The FPGA control module is the core of this design.

2 Design and implementation of FPGA controller
The development software of this design uses Altera's QuartusⅡ integrated development environment, adopts a top-down design method, and combines module design with Verilog-HDL description input method to facilitate program maintenance and upgrade. The overall design of the FPGA controller is shown in Figure 2.

As shown in Figure 2, FPGA control programming mainly consists of six modules: key request module, state control module, motor drive module, display and alarm module, switch door control module, and frequency division module. The signals and functions of each module are as follows:
Module 1: Key request module
The interface signals of this module are shown in Table 1, and the module functions are as follows:
(1) Use the latch to store the input request signal and clear it to 0 when the request is met. For the convenience of data representation, the suffixes 0 to 3 in this design represent the 1st to 4th floors respectively.
(2) According to the running status of the elevator, according to the principle of direction priority and cyclic execution, the floor signal of the next stop of the elevator is extracted from the request signal and output. If the current floor is 2 and the state is rising, then the judgment priority is: p2/up2→p3/down3→down2→downl→p0/up0.
(3) When there is no request signal, the next stop floor is 0.

Module 2: State control module
This module is the core control module of the system design. This paper divides the elevator operation into 4 states: ascending, descending, stopping, and idle. The state transition diagram of the control system is shown in Figure 3.

When the system restarts (res=1), it enters the idle state (Idle). In the idle state, the output signal posit=up=down=open=0. When the input signal goto is 0, it remains in the idle state; when the goto signal is not 0, it enters the rising state (Stop). When the first floor rising signal is triggered, it enters the stop state. In the stop state, the rising edge of the open signal triggers the elevator door to open; up=down =0, posit=goto. During the elevator door opening delay period (dooropen=1), it remains in the stop state; when the elevator door is closed (dooropen=0), the next floor is determined. If it is greater than the current floor, it enters the rising state; if it is less than the current floor, it enters the descending state. In the ascending state, up=1, updown=01, posit=goto, triggering the motor control module to drag the motor up. The floor reaches the signal, causing the system to enter the stop state. The descending state is the same. The interface signals of this module are shown in Table 2.

Module 3: Motor control module
The input signals of this module are: rising trigger signal (up), falling trigger signal (down), current floor (posit) and next floor (goto), and the output signal is: 4 motor drive signals with different phases. The module is triggered by the lifting signal, and generates 4-phase motor drive signals P[3:0] through the motor state controller, which are output to the motor drive circuit. Its frequency determines the motor rotation, and its phase determines the direction of motor rotation. Each frequency signal of P[3:0] is provided by the divider module.
Module 4: Display module
The function of this module is used for the seven-segment code display or LED display of the elevator floor (posit) and the elevator operation status (updown). And the alarm and display of the overload signal (over).
Module 5: Door control module
This module is used to control the elevator door state. The door opening is triggered by the input door control signal open signal (doorstat=1). After a delay, the elevator door automatically closes (doorstat=0). If the elevator is overloaded (over=1), the elevator door will not close, and the elevator will remain in the open state until the overload signal is cleared.
Module 6: Frequency division module
The frequency division module is used to divide the system clock signal to generate various frequency signals provided to the motor control module.

3 Simulation verification
This design adopts modular design at the top level, and each module uses VerilogHDL hardware description language. The top-down design method is convenient for program error checking, upgrading and improvement. This design can realize elevator control on any floor with slight modification. Functional simulation and timing simulation of the circuit generated after analyzing, compiling, synthesizing and wiring the designed program can obtain logical values ​​that meet the design requirements. The timing simulation waveform is shown in Figure 4.

As can be seen from Figure 4: the controller can always effectively store the request signals of each floor, and can execute the requests of each floor according to the direction priority and cyclic order. The status of each signal meets the design requirements. The signal delay is 10 ns, which is within the allowable range.
The hardware implementation of this design adopts the Kangxin KX_7CH minimum system version. The program is locked by pins and programmed to download to the device. After testing, the logic is completely correct and meets the design requirements.

4 Conclusion
The digital circuit design method based on FPGA has huge advantages in reliability, volume and cost. It has become one of the main means to realize digital circuits. The four-story elevator controller designed in this paper is suitable for any floor with a little improvement. It has strong flexibility, reliable operation, and strong adaptability and practicality.