Design of ultrasonic guided wave excitation signal generator based on SoPC

Abstract: Based on SoPC technology, a signal generator specially used to excite ultrasonic guided waves in pipelines is designed. The design method of the DDS IP core dedicated to guided waves is emphasized. The generator uses the MicroBlaze soft-core processor as the control core, and the single-chip FPGA is supplemented by a small amount of necessary peripheral hardware circuits, which is easy to expand and upgrade. The experimental results show that the output signal has high accuracy, low noise, good stability, and continuously adjustable frequency, which can be easily applied to pipeline ultrasonic guided wave detection.
Keywords: SoPC; MicroBlaze; DDS; ultrasonic guided waves; excitation signal

In pipeline defect detection, ultrasonic guided wave detection technology has the characteristics of low attenuation along the propagation path, long propagation distance, and the particle vibration caused by it can spread throughout the interior and surface of the component, thus showing greater advantages compared with traditional non-destructive testing methods [1]. Ultrasonic guided waves have multi-modal and dispersion characteristics during propagation. If the excitation source is not properly selected, the guided waves will be seriously dispersed, making the echo signal extremely complex, which is not conducive to defect analysis. According to the waveguide dispersion characteristic curve, in the range of 50 kHz to 500 kHz, the L(0,2) mode ultrasonic guided wave has the fastest and most stable propagation speed and almost no dispersion. Using a Hanning window to modulate a single audio signal with a certain number of cycles in this frequency band to form a narrow-band pulse as the excitation source, the ultrasonic guided wave dominated by the L(0,2) mode can be stimulated to minimize the adverse effects of dispersion [2].
At present, there are many designs for ultrasonic guided wave excitation signal generators. One is to use a multi-function function generator such as HP33120A [3]. Due to the limited storage length of HP33120A, interference will occur between pulses during long-distance detection, and the maximum modulation frequency is not high [4]. The second method is to use a single-chip microcomputer to control the DDS chip design, which has high precision, but weak customization, and generally requires more than two DDS chips, which is expensive. Another method is to use a high-speed single-chip microcomputer to control the D/A conversion chip to directly output the signal, which is convenient and easy to implement, but the precision is low, the excitation frequency is limited by the frequency of the single-chip microcomputer, and it is difficult to achieve continuous adjustment. In order to solve the shortcomings of the above design schemes, this design uses the MicroBlaze soft-core processor as the control core on the Xilinx FPGA (field programmable gate array), and draws on the direct digital frequency synthesis DDS (Direct Digital Frequency Synthesis) technology to provide a SoPC (System on Programmable Chip) implementation method for generating L (0,2) mode ultrasonic guided wave excitation signal source. The obtained excitation source has high precision, the number of cycles of the single-tone sine wave under Hanning window modulation is adjustable, and the frequency is continuously adjustable.
1 System overall solution design
This system uses the Xilinx Spartan 3E-Starter development board as the hardware platform. This development platform has rich peripheral resources, and system design can be realized by adding a small number of peripheral devices. The Spartan 3E series FPGA is the most cost-effective FPGA chip of Xilinx, which can better meet the high integration and low cost of products [5]. Its internal MicroBlaze soft-core processor adopts a powerful 32-bit pipeline RISC structure, including 32 32-bit general registers, 2 32-bit special registers, and can have a 3/5-stage pipeline. The clock frequency is up to 150 MHz. Based on IBM CoreConnect technology, it provides rich interface resources. Among them, the PLB (processor local bus) bus provides access to on-chip peripherals, external memory, and algorithm modules written based on hardware description language, and together with other peripheral IP cores, completes the embedded SoPC development. The SoPC implementation structure of the ultrasonic guided wave excitation source is shown in Figure 1.

FPGA implements all digital circuit parts. MicroBlaze soft-core processor is the control core of the system. It accesses the program storage space BRAM through LMB (local memory bus) and mounts the required IP core through PLB bus. The GPIO interface is instantiated to connect the keyboard and is responsible for the frequency setting of the excitation signal. LCD1602 is used to display the current frequency value. The self-written DDS IP is the core of the system waveform generation and directly generates the excitation source waveform. MDM is the debugging module of the system, and RS232 is used to communicate with the PC or program debugging. The digital clock manager DCM (Digital Clock Manager) IP core that comes with Xilinx embedded development kit EDK is used to divide the 50 MHz input clock to provide stable 5 MHz and 50 MHz clock signals for the DDS module and the external high-speed digital-to-analog conversion chip DAC902 respectively. The program is downloaded to the BRAM inside the FPGA through JTAG, or stored in the off-chip PROM. The digital signal generated by the FPGA is converted into an analog signal by DAC902, and then denoised by a low-pass filter to obtain a high-quality ultrasonic guided wave excitation signal source.

2 Ultrasonic Guided Wave DDS IP Core Design
2.1 DDS Algorithm Principle
DDS generates waveforms based on the sampling theorem through a lookup table method. Usually it is a sine wave, cosine wave, triangle wave or square wave, etc. The complete DDS structure diagram is shown in Figure 2. Driven by the reference clock, the N-bit phase accumulator accumulates the phase of the frequency control word K, and the obtained phase code addresses the waveform memory to output the corresponding waveform amplitude value. This value is sent to the DAC and the low-pass filter LPF to realize the conversion of the quantized amplitude to a smooth signal. When the phase accumulation value is greater than 2N, the phase accumulator generates an overflow, and the overflow frequency is the output frequency of the DDS. The output signal frequency fout can be expressed as:

According to the principle of DDS, the number of bits N of the phase accumulator determines the accuracy of DDS. The larger the value of N, the finer the frequency interval of DDS. However, as the value of N increases, the required ROM capacity will also increase exponentially. In fact, in general systems, the number of bits m of the D/A converter is fixed, and the output bit number N=m+2 of the accumulator is usually selected to meet the needs [6]. In the design, DAC902 is 12 bits, the accumulator is 14 bits, and the maximum amplitude of the modulated pulse is 212, that is, 4096. With the help of Matlab, a narrow-band pulse waveform modulated by a 10-cycle sine wave with a Hanning window is generated, as shown in Figure 3.

This design is based on DDS technology and uses Verilog HDL hardware description language to design a DDS module that directly generates waveguide excitation waveforms. The top-level principle is shown in Figure 4.

The 50 kHz~500 kHz frequency of the L(0,2) mode ultrasonic guided wave refers to the frequency of the single audio signal (as shown in Figure 3, 10 cycles, assuming the single audio frequency is f0), not the DDS output frequency fout. From Tout=10T0, we get fout=f0/10. Therefore, the DDS output fout should be 5 kHz~50 kHz. The system master clock is 50 MHz. When the maximum DDS output frequency is 50 kHz, in order to achieve a 0.3 kHz (single audio 3 kHz) step value, the number of sampling points of the 10-cycle narrowband pulse should be no less than 100 points to reduce distortion, then the clock frequency must be greater than 4.9 MHz. Divide the system master clock by 10 to get a 5 MHz DDS clock frequency. The frequency control word can meet the requirements by taking 8 bits.
The accumulator module Accu accumulates the frequency control word K and sends the lower 14 bits of the result sum[13:0] to the next level Reg register as the ROM address. The highest bit sum[14] of Accu is the judgment bit. During the accumulation process, when the phase sum[14] is 1, the accumulator is cleared to complete a pulse emission. Then a counter is used to implement the delay function so that the excitation pulse is emitted every 1 ms.
The ROM module is directly customized using the ROM IP core in ISE. If multiple ROMs are added to the system, each ROM is loaded with modulated pulses of different periods, so that the period of the excitation source can be adjusted. With the help of Matlab, the narrowband pulse in Figure 3 is quantized into a 12-bit fixed-point waveform value, forming a .coe file and loading it into the ROM.
When the frequency control word K is set to 23, the output frequency fout is equal to 7 kHz, corresponding to a single audio signal of 70 kHz. The Modelsim simulation waveform is shown in Figure 5.

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3 System Hardware Implementation
3.1 Peripheral IP Core Mounting
Use EDK's XPS to create a MicroBlaze hardware platform. Use the Base System Builder Wizard to quickly add configurations such as RS232, GPIO, BRAM, etc. For the self-written DDS module, use the Create/Import Peripheral tool to appropriately modify the two automatically generated files, user logic and IPIF, to mount your own logic module on the PLB bus without having to worry too much about the protocol and interface logic between the custom IP and the PLB bus. Add the built-in DCM clock management module in XPS to provide accurate and stable clock input for the DDS IP and DAC. Finally, assign addresses to all peripherals and establish port connections.

4 Software Design
The software part is written in C language in SDK, mainly including initialization, GPIO port keyboard value reading, LCD display, DDS frequency word input and adjustment, etc. Since the waveguide frequency is between 50 kHz and 500 kHz, the span is large. In order to facilitate actual detection, the frequency coarse adjustment and fine adjustment functions are designed. The system keyboard includes the set key (Set), coarse adjustment key (Adjust), fine adjustment key (Fine), confirmation key (OK) and reset key (Reset). After power-on, the frequency control word K is the initial value 16, and the system generates a 50 kHz default frequency excitation signal. Each time the coarse adjustment key (Adjust) is pressed, the K value increases, corresponding to the base frequencies of 70 kHz, 120 kHz, 170 kHz, etc. Use the fine adjustment key (Fine) to make fine adjustments with a step value of 3 kHz. The K value is assigned to the DDS module through the write register statement DDS_IP_mWriteReg to generate the corresponding frequency excitation signal. The program flow is shown in Figure 8.

5 Analysis of experimental results
After the system is powered on, the excitation frequency value is selected as 70 kHz on the keyboard, and the output signal is collected and analyzed using the virtual oscilloscope of the NI PCI-5102 digitizer. The captured excitation signal is shown in Figure 9. From the panel parameters, it can be seen that the maximum amplitude of the waveform is 1.5 V, and the narrowband pulse width of the single audio signal containing 10 cycles is about 0.142 ms. Change the keyboard input and perform FFT spectrum analysis on the output signal, as shown in Table 1. The experimental results show that the excitation signal generated by this design has high accuracy, pure waveform, good performance, and continuously adjustable frequency, which meets the design requirements well.

Using SoPC technology, a new design method for ultrasonic guided wave excitation signal generator is given. The implementation process of the waveguide dedicated DDS module is discussed in detail. The main functions of the system are integrated into a single-chip FPGA, which reduces the peripheral circuits, has a small size, low power consumption, strong anti-interference ability, is easy to expand and upgrade, and effectively reduces the design cost. The generated excitation signal has high accuracy, good stability, and continuously adjustable frequency. This design can be easily applied to pipeline ultrasonic guided wave defect detection, and provides the possibility for the development of miniaturized and integrated guided wave detection systems.