Design of TV Tracking System Based on TMS320DM642

In modern air defense fire control systems, searching, discovering and tracking targets is the basis of the entire system. The most important means of detection and reconnaissance is still radar, but it is an electromagnetic wave emission source. While obtaining target information, it also exposes itself and is vulnerable to anti-radiation missile attacks. In addition, it cannot track low-altitude targets and is affected by lobe touchdown, multipath effect, and ground interference, which seriously affects the normal functioning of its functions. The

TV tracking system uses a high-precision camera to obtain target scene information, converts it into a video signal and sends it to the monitor. The servo platform is guided by the console (or by radar) to make the target enter the capture window, and the target is captured and detected in real time. The pitch and azimuth error signals of the target relative to the optical axis are obtained, and the movement of the servo platform is controlled to achieve tracking of the target. The TV tracking system has the advantages of high resolution, visible image, good anti-interference performance, and low cost. It is widely valued in the military and has become a powerful supplement to radar in air defense fire control systems.

DSP has been widely used in the fields of video and image processing, especially in embedded systems. DM642 (DigitalMedia) is a high-performance fixed-point DSP chip for video/image processing launched by TI in 2003. Compared with the previous C64x, its main frequency reaches 500-600MHz, and the highest can reach 720MHz. The instruction execution speed is as high as 4000-4800 MIPS, and the instruction set is fully compatible with C64X. In particular, it has 3 independently configurable video ports, which can be independently configured as video acquisition or display ports, all of which support a variety of acquisition/display schemes and video standards, support RAW video sets, and can achieve seamless connection with general video codecs. In addition, the video signal can be quickly transmitted between the memory and the video port using EDMA.

System Principle and Design

Most of the functions of the television tracking system in the early or active weapon systems of various countries are realized by hardware circuits, with complex structures, high requirements on environmental conditions, and serious obstacles to the realization of complex search and tracking algorithms. The search and tracking capabilities are low, especially not suitable for modern air raids with full airspace, multiple sorties and multiple levels. With the development of digital technology and graphic image processing technology, TV tracking system is also moving towards digitalization, as shown in Figure 1.

This digital TV tracking system adopts advanced DSP digital processor and modular design concept. It not only realizes modularization in overall design, but also adopts modularization in system hardware and software design. The whole system is divided into 6 functional modules in hardware: image acquisition module, target tracking and recognition module, communication control module, servo control module, character and information superposition module and power module; the software can be divided into image acquisition module, image processing module, recognition and tracking module, display control module and main control module in terms of function. [page] The

main processing work of the TV tracking system is completed by the core processing board. The processing chip adopts TMS320DM642 DSP. Its significant feature is the integrated video input and output port, which is connected to the peripheral video encoding/decoding chip. The decoding chip collects TV signals through CCD, converts them into analog-to-digital signals, and processes them with tracking algorithms to obtain the offset of the target center of mass to the center of the field of view, which is sent to the servo control module to drive the pan-tilt head to rotate and realize automatic tracking. The communication control module receives the fire control system parameter signal output by the fire control computer and completes the superposition with the video signal through DSP control. The specific superimposed signals include target height, distance and speed, as well as the crosshairs at the center of the field of view. In this system design, an FPGA located between the DSP and the video encoding chip is used to complete this superimposed function. Since this part of the circuit focuses more on the function realization of the FPGA, the specific design will not be described in detail in this article.

DM642 video port hardware design

This system combines the characteristics of DM642 and uses two video ports to connect the video decoding chip and the video encoding chip (SAA7115 and SAA7105H of Philp Company) respectively, directly building a video acquisition and display channel. The programming of the encoding/decoding chip is set through the I2C bus. The specific technology can be found on the relevant website. This article focuses on the design ideas of this system.

Figure 2 Main hardware circuit for video acquisition and display

Figure 2 is the main hardware circuit of the video acquisition and display of this system. Since DM642 itself is designed for video/image processing, it has highly integrated video acquisition unit and display unit, supports mainstream codec chips, and effectively simplifies the peripheral circuit. Here are some points to note:

1) The video data input of this system adopts color PAL format, and the output is black and white PAL format. YUV422 encoding is used in the middle, and the data bit is 8 bits.

2) The video port 0 (Video Port0) of DM642 and its supporting control signals first pass through the signal holding and transceiver conversion circuit, and then connect to the corresponding pins of the decoding chip SAA7115. This system is suitable for all major standard composite videos, and its internal registers are controlled through the I2C bus to select functions. The specific operation functions are encapsulated in the software driver part.

3) The video port 2 (Video Port2) of DM642 is used for video display. This encoder can encode RGB, HD, NTSC, and PAL, and can also encode S-terminal video through programming. Its programming is also carried out through the I2C bus.

4) Similar to the decoding circuit, the DM642 video port 2 can be directly connected to the encoding chip, but the encoding display circuit of this system connects the DSP and the encoder (SAA7105 of Philp) through an FPGA (XiL inx XC2S300E). On the one hand, it superimposes characters, wave gates and other information on the video signal to be displayed, and on the other hand, it is used to perform logical processing on various control signals, making full use of the FPGA space and avoiding additional logic control circuits.

5) The control signals of the DM642 video port and the encoding and decoding chip control signals mainly include line synchronization, field synchronization and clock signals, especially paying attention to ensuring the 33Ω matching resistance of the video signal.

Software design of DM642 video operation

Considering the versatility and compatibility, the driver of the video port part of DM642 in this system is divided into two parts: the general driver part for the video port and the dedicated driver part for the video processing peripherals. The former is fixed for a fixed model of DSP and is provided by TI, and the user does not need to change it; the latter depends on the video peripherals designed by the user, and is generally only related to the peripheral hardware, and its related parameters and functions are encapsulated by the user. The two are connected as one through the extended device controller (EDC) inside the DSP, and are jointly responsible for the acquisition, transmission, and processing of video signals. [page]

For TI's DSP development environment CCS, the above two parts of the driver can be further encapsulated into a FV ID (frame video) driver model. As a general I/O model for video port operations, it mainly includes the following two types of function models:

1) The general driver part mainly completes the configuration, reading and writing of the DSP chip to its video port. It is mainly divided into overall port configuration, single acquisition/display channel configuration, and video port interrupt configuration. Its parameter types are stored in the corresponding structures in Vport.h, VportCap.h, VportDis.h, and Vport.h. Users can refer to the literature [1] to select appropriate parameters when developing programs.

2) The dedicated driver part, whose main task is to initialize the video encoding/decoding chip and select the working mode, for example, this system uses SAA7105 and SAA7115 of PHILP as video encoding/decoding, so it is necessary to set its encoding/decoding format, cache mode and other aspects. Generally, its configuration parameters are defined as a structure for calling in the project. Since the extended device controller encapsulates the general driver part into a series of API interfaces, it can be called when the user writes the dedicated driver part. The main API information is stored in EDC.h. For detailed information, please refer to the TI website. The author focuses on the method of video signal acquisition and display in DM642EVM. In order to complete the establishment and management of video streams, the main work is shown in Figure 3.

Figure 3. Video signal flow establishment and management

1) Define the common properties of the video port in the system configuration file (BIOS configuration file cdb), establish encoding channels and decoding channels as needed, and specify the working parameters of each channel. For specific parameter types, see Vport Cap.h and Vport Dis.h.

2) Since EVM has encapsulated the video peripheral driver (dedicated driver part) into the FV ID library, users only need to refer to the structures in saa7105.h and saa71105.h to establish parameter objects (similar to class objects in VC++) for each video peripheral to make it work in the selected mode.

3) In the CCS project execution function, set the trigger mode for video acquisition and display. Generally, video acquisition uses the interrupt mode. When the buffer area of ​​the acquisition channel is saturated, an interrupt request is issued. The video display trigger generally uses the default mode.

4) In the response function, first switch its cache pointer to the backup cache, and then process the current data area. In particular, for
PAL video, the acquisition program automatically reorders the odd and even field pixels. The one-dimensional cache data sequence directly corresponds to the pixel values ​​arranged row by row from the upper left to the lower right of the video. A single pixel value is a structure object that contains all its color features, which is convenient for the image processing function to read. Then write the processing result into the cache area of ​​the display channel. After writing, switch the cache area of ​​the display channel to the backup cache. After starting the display task, the display encoding circuit automatically reads its cache area and encodes and outputs according to the set mode.

Conclusion

TMS320DM642 is a high-performance fixed-point DSP chip for video/image processing. Its hardware design and software construction meet the professional needs of the video/image field. It and its subsequent models have a wide range of application prospects in this field. Based on the design of a TV tracking system, the author focused on the principles and implementation methods of its video port related software and hardware, providing a reference for software development and hardware circuit design for the development of other video/image processing systems, especially the establishment and management methods of standard TV signal streams. After design and debugging, the acquisition, caching, processing and display of standard TV (PAL, NTSC) were successfully realized. The experimental results show that this method is feasible and the system runs stably.

The main problem of this system design is that the optimization efficiency of the C language compiler in the development environment is very low. Although assembly language is difficult to write, and the readability and maintainability are poor, in order to ensure the execution speed of complex processing algorithms, the next step is to use assembly language to write some core programs.

References:
[1] Texas Instruments. TMS320DM642 video/imaging fixed-point digital signal processor [Z]. Texas Instruments Incorporated, 2003.