Implementation of digital frequency correction based on CORDIC algorithm and FPGA

In a radio receiver system, the signal received by the receiver often experiences frequency offset due to the influence of factors such as the motion of the transmitter, the motion of the receiver, and the dynamic change of the standard frequency over time, so frequency offset correction is required. In a spread spectrum communication system, the frequency offset correction circuit can eliminate the influence of the intermediate frequency offset on the capture of the receiver spread spectrum code and the data demodulation performance, thereby improving the performance of the receiver.

In the frequency offset correction circuit, it is usually necessary to generate cosine and sine signals according to a given phase. The most important implementation technology is the CORDIC (Coordinate Rotation Digital Computer) algorithm. This article will analyze the principle of the CORDIC algorithm and its FPGA implementation method in detail.

1 Basic Principles of CORDIC Algorithm

In a rectangular coordinate system, suppose there is a vector (x, y), and a vector (x1, y1) is obtained by rotating it counterclockwise by φ degrees. The algebraic relationship between the two vectors is:

In formula (1), if the rotation angle φ satisfies the condition: tanφ=±2-i, the multiplication operation in formula (1) can be converted into a shift operation, which is easy to implement in FPGA. Figure 1 shows a schematic diagram of vector rotation in rectangular coordinates. If the angle to be rotated is θ, it can be completed by rotating a series of predetermined angles αi n times.

(2) In the formula, di represents the direction of each rotation, αi. Since each rotation is a predetermined angle value, cosαi is a constant, and the processing of each iteration in n rotations can be expressed as:

In general, when the number of rotations is large enough, Ki is generally a constant. Since this constant can be multiplied in the final calculation result during implementation, Ki in formula (3) can be removed. In this way, the iterative equation only contains shift and addition operations, which greatly simplifies the complexity of FPGA implementation. Since another equation is required to determine the sign of di, the variable zi is introduced to represent the accumulated value of each rotation of the predetermined angle:

In this way, the iterative equation of the CORDIC algorithm can be expressed as:

The final result is:

In the frequency offset correction circuit, it is usually necessary to generate a cosine signal cosθ and a sine signal sinθ according to a given phase θ. In order to generate standard sine and cosine signals without amplification, the y component (i.e., yo) of the input vector can be set to 0 and the x component (i.e., xo) to 1/An. In this way, equation (6) can be simplified to:

It can be seen that after the above processing, the input phase zo can be converted into standard sine and cosine signals. [page]

2 FPGA Implementation of CORDIC Algorithm

The most commonly used methods for implementing the CORDIC algorithm using FPGA are iterative algorithms and pipeline-based algorithms. The CORDIC iterative algorithm has only one level of iteration unit. Driven by the system clock, the output of the iteration unit can be used as the input of this level, and the calculation is completed through the same level of iteration. The hardware overhead of the iterative algorithm is very small, but it takes multiple clock cycles to complete a CORDIC operation, and its operation speed is relatively slow.

In the CORDIC pipeline structure algorithm, each level of CORDIC iterative operation uses a separate operation unit. When the pipeline is filled, a set of results will be calculated immediately in each clock cycle, so the calculation speed is very fast.

Although the calculation speed of pipeline structure algorithm is very fast, its accuracy is limited by the number of pipeline stages. To improve the accuracy, the number of pipeline stages must be increased, which increases the hardware overhead. Therefore, the selection of pipeline stages must take into account the requirements of speed and accuracy.

3 Implementation scheme and simulation results

3.1 Implementation plan

The pipeline flow chart of the CORDIC algorithm is shown in Figure 2. This method uses a 7-stage pipeline, so the calculation speed can be greatly improved.

3.2 Simulation Results

The simulation results of the sine-cosine signal generator based on the CORDIC algorithm are shown in FIG3 . As can be seen from FIG3 , the algorithm can realize standard sine waves and cosine waves and can be directly used as a frequency offset correction unit.

4 Conclusion

This paper analyzes the working principle of the CORDIC algorithm and provides a solution for implementing digital frequency correction based on the CORDIC algorithm and FPGA. The simulation results show that this method can realize standard sine and cosine wave signals and can be directly used as a frequency deviation correction unit to correct digital frequency signals.