Design and implementation of audio switching mixing matrix

The audio switching and mixing matrix is ​​the core equipment of various conference, broadcasting and command systems. It connects different audio input and output devices to realize the switching and mixing functions of audio, and realizes the control and scheduling of audio signals.
Traditional audio matrices are usually designed based on analog switch circuits, which are complex in design and difficult to implement, and are not suitable for building medium and large-scale switching matrices. Moreover, most matrices do not have volume adjustment and signal mixing functions, and need to be used with mixing consoles and signal mixers.

This paper proposes a design scheme of audio switching and mixing matrix based on FPGA (Field Programmable Gate Array). This scheme is based on the principle of switching technology, adopts digital audio signal sampling and processing technology, constructs switching and mixing matrix, realizes the switching and mixing of 16 × 16 audio signals; the design and implementation are easy, and the system switching capacity can be reduced or increased according to system requirements, and the audio signal sampling accuracy and sampling rate can be set; the volume of each input and output signal can be controlled independently; it also has the characteristics of low input and output delay, high isolation between channels, and good sound quality.

1 Mathematical Model of Audio Switching Mixing Matrix

1.1 Switching System Principle

Switching technology originated from telephone communication. Its basic task is to achieve effective end-to-end transmission of information between users in a large-scale network. The principle of switching technology is to controllably send data from the source to the destination through a set path.

For audio systems, switching refers to forwarding audio signals from the input through a series of nodes to the output.

1.2 Exchange mixing matrix mathematical model

Based on the switching technology principle described in 2.1, a general mathematical model of the switching system can be constructed. The multi-input and output switching system is abstracted as a matrix P, and its input and output signals are abstracted as two vectors (x, y). The function of the switching system is to convert the input vector into the output vector through matrix operations:

Where pij ∈ [0, 1] represents the corresponding relationship between input and output. n and m represent the number of input and output signals respectively. When n = 1, the system is a single-input system; when n > 1, the system is a multi-input system.

When m = 1, the system is a single-output system; when m > 1, the system is a multi-output system.

For an audio switching and mixing system, pij represents the corresponding relationship between a certain input and a certain output, as well as the volume information. Finally, a single output signal yj can be expressed as:

The core technology of this solution is to convert multi-channel analog audio input signals into digital input vectors and construct a digital switching mixing matrix. By operating the matrix, a digital output vector is obtained, and the output vector is converted into an analog audio output signal and distributed to each output port, finally realizing an audio switching mixing matrix.

Here, let vectors A and B be the input and output volume control vectors, respectively, and matrix Q be the control matrix. Then the exchange matrix P is transformed into:

In summary, the final mathematical model of the system is:

Where qji = 0, 1.

From formula (4), we can see that the final result yj of the j-th output is:

2 System Design Overview

2.1 System signal flow

According to equation (4) and equation (5), the system signal flow chart can be constructed, as shown in Figure 1.

Figure 1 Signal flow chart of the switching hybrid matrix system.

ai and bj are implemented by the volume control chip, the digital/analog and analog/digital conversions are implemented by dedicated chips respectively, and the matrix Q and multi-way adder are implemented by FPGA.

The system switching capacity is set to 16 × 16, that is, n = 16, m = 16. The switching capacity can be expanded or reduced according to different system requirements.

2.2 System Hardware Design

It can be seen from the system signal flow chart that the overall hardware module of the system consists of input volume control, digital/analog conversion, switching hybrid matrix, analog/digital conversion, output volume control, etc. The overall hardware module block diagram of the system is shown in Figure 2.

Figure 2 is a block diagram of the overall hardware module structure of the switching hybrid matrix.

The input volume control chip is PGA4311, which has a gain adjustment range of 31.5 dB to -95.5 dB and is controlled by SPI bus.

The input analog/digital conversion chip uses PCM4204, which uses an IO interface to control the working mode and parameters. The specific setting method can be found in the literature.

The output digital/analog conversion and volume control chip uses PCM1681, which works in slave mode and is controlled using the I2C interface. For specific settings and usage methods, see the reference.

By setting the analog/digital and digital/analog conversion chips, the sampling accuracy and frequency of the digital audio signal can be adjusted according to system requirements.

The sampling frequency of the scheme example described in this article is 97.7 kHz, the sampling accuracy is 24 bits, and the left-aligned PCM encoding method is used for transmission. The transmission timing diagram is shown in Figure 3.

Figure 3 PCM encoding transmission timing (left aligned).

2.3 FPGA and its programming

The FPGA contains serial/parallel conversion, switching matrix, mixing, parallel/serial conversion, clock module and matrix control module, and its internal module block diagram is shown in Figure 4. The FPGA uses Altera's EP2C35 chip, and its specific parameters can be found in the literature.

2.3.1 Clock module

The function of the clock module is to provide a unified global clock for the serial/parallel and parallel/serial conversion modules. The system requires three clock signals: system clock (SCK), bit clock (BCK) and channel clock (LRCK). The frequency of each clock is determined by the sampling frequency (fS):

Figure 4 FPGA internal module block diagram.

In this system, the sampling frequency fS is 97.7 kHz, and the above clocks are generated by dividing a 50 MHz external clock signal.

A 9-bit accumulative counter Q is established in the module. An incremental count is completed on the rising edge of the clock signal. When the value reaches the full value 111111111, Q is set to 0 in the next clock cycle. The XCLK, BCK, and LRCK outputs are connected to the 0th, 2nd, and 8th bits of the count output, respectively, and the 3rd to 7th bits are combined into another count output S_Count, which is used to control the bit count of the serial-parallel and parallel-serial conversion. Therefore, the actual generated fSCK is 25 MHz, fBCK is 6. 25MHz, and fLRCK and fS are 97. 7 kHz.

2.3.2 Input serial/parallel conversion module

This module is responsible for converting the serial PCM code input by PCM4204 into parallel data and sending it to the switching matrix module for processing. A 32-bit shift register (S_Buf) is built inside the module to store serial data and control the parallel output according to the action of the channel clock (LRCK). The serial/parallel conversion process is shown in Figure 5.

Figure 5 Serial/parallel conversion flow chart.

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2.3.3 Matrix Control Module

The function of this module is to receive commands from the external control unit and control the matrix to implement the switching operation. FPGA reserves 10 GP IOs as enable control ports, which are defined in Table 1.

Table 1 Matrix control port definition

The output of the module is 16 groups of 16-bit parallel data, forming a matrix table. Each group of data represents an output port, and each bit in the group represents a corresponding input port. The elements in the table represent the connection relationship between the corresponding input and output, 0 means disconnected, and 1 means connected.

When using, first select the input and output ports that need to be operated and the operating status, then input a high level to EN to trigger the control circuit to work and connect or disconnect the selected input and output signals.

2.3.4 Hybrid Module

The module consists of two parts: data buffer register (AdderBuf) and adder (Adder). The data buffer register reads the state of the control port (Sel), and then determines whether each input is valid, that is, whether it is sent to the output port. If an input port is valid, the port data is directly sent to the adder; if it is invalid, the data 0 is sent.

2.3.5 Switching matrix module

The working principle of the switching matrix is ​​a 16-to-256 distributor, which distributes each input into 16 channels and sends them to the mixing module of each output. Its structure is shown in Figure 6.

Figure 6 Switching matrix module structure diagram.

2.3.6 Output parallel/serial conversion module

This module is responsible for converting the 24-bit parallel data output by the mixing module into a serial PCM code that can be received by PCM1681. The data transmission format is the same as that of PCM4204. A 24-bit shift register is established inside the module to generate serial output and read parallel input according to the action judgment of the channel clock (LRCK). The parallel/serial conversion process is shown in Figure 7.

Figure 7 Parallel/serial conversion flow chart.

3 System Simulation and Implementation

3.1 System Simulation

The overall port and module block diagram of FPGA is shown in Figure 8.

Figure 8 FPGA overall port and module block diagram.

A 50 MHz clock signal is input from the clock input terminal (CLK); a control signal is sent to the switch control port to connect In_0 to Out_0, In_1 to Out_1, ..., In_7 to Out_7. The control signal input is shown in Figure 9.

Figure 9 Control signal input.

Input the hexadecimal serial data 000000 at the left channel input timing of the first serial signal input terminal (In_0), and input 111111 at the right channel input timing; similarly, input 222222 at the left channel input timing of In_1, and input 333333 at the right channel input timing; input EEEEEE at the left channel input timing of In_7, and input FFFFFF at the right channel input timing. The serial data input is shown in Figure 10.

Figure 10 Serial data input.

The serial output end of the system has corresponding data output. The left channel output data of Out_0 is 000000, and the right channel output data is 111111, which is consistent with the In_0 input data; the left channel output data of Out_1 is 222222, and the right channel output data is 333333, which is consistent with the In_1 input data; ?; The left channel output data of Out_7 is EEEEEE, and the right channel output data is FFFFFF, which is consistent with the In_7 input data.

The serial data output is shown in Figure 11.

Figure 11 Serial data output.

Change the control port data to connect the left channel input of In_1 (data is 222222) and the right channel input of In_2 (data is 555555) to the left channel output of Out_0. As shown in Figure 3-5, the serial data output of Out_0 becomes 777777. The serial data mixed output is shown in Figure 12.

From the above simulation results, it can be seen that the overall FPGA design can realize the exchange and mixing of serial digital audio signals and meet the expected design requirements.

Figure 12 Serial data mix output.

3.2 System Implementation

A real photo of the exchange mixing matrix is ​​shown in Figure 13.

Figure 13: Photo of the switching hybrid matrix

During the physical test, the switching and mixing matrix is ​​first connected to the embedded control system and controlled by the embedded control system. The audio signals played by computers, MP3, portable CD players, signal generators, etc. are used as input sources, and speakers, headphones, oscilloscopes, etc. are used as output devices to test the switching, mixing and volume adjustment functions. After *testing, the output audio signal has no obvious distortion. When multiple audio signals are mixed and output, good signal quality can still be guaranteed. The measured waveform of input and output delay is shown in Figure 14, which is about 620μs. The amplitude-frequency characteristic curve obtained by point-by-point measurement is shown in Figure 15, and the passband is 20 Hz to 38. 44 kHz.

Figure 14 Input and output delay measurement waveforms.

Figure 15 Amplitude-frequency characteristic curve.

The test results prove that the switching and mixing matrix can correctly accept the commands of the control system and complete the functions of switching, mixing and volume adjustment of audio signals.

4 Conclusion

Aiming at the application requirements of audio switching system, this paper proposes a design scheme of audio switching hybrid matrix based on FPGA, describes and simulates the software and hardware design, and completes the physical production and testing.

The solution described in this article uses FPGA as the core device of the switching hybrid matrix, so it has strong versatility and can reduce or increase the switching capacity, configure the audio signal sampling frequency and sampling accuracy according to actual needs.

Through simulation and physical testing, the FPGA-based audio switching and mixing matrix can realize the exchange, mixing and volume adjustment of audio signals. It also has the characteristics of low delay, high isolation and good sound quality. It can be used in various conference, command, communication and other occasions.