With the inventor of RISC-V in charge, SiFive successfully held its first three-city tour across the country

Recently, SiFive, the main supplier of RISC-V IP, successfully completed a technology forum tour in Shanghai, Beijing, and Shenzhen. Professor Krste Asanović, the main inventor of RISC-V, co-founder and chief architect of SiFive, and SiFive executives Gang Zhijian participated in the three-city tour and talked about global RISC-V trends and the development of RISC-V in China's semiconductor industry.

Professor Krste Asanović (right), co-founder and chief architect of SiFive, and Gang Zhijian (left), senior vice president of corporate marketing and business development at SiFive, were interviewed by the media

Currently, major market leaders such as Google, Samsung, Qualcomm, Intel, and Microchip, as well as many innovative companies, are working closely with SiFive and have successfully introduced SiFive RISC-V solutions; SiFive RISC-V processors also cover artificial intelligence, machine learning, automotive High-performance computing such as electronics, data centers, mobile computing, and consumer electronics, as well as aerospace and other application fields. In China, many customers have chosen SiFive's products.

In addition to SiFive’s product promotions, RISC-V’s ecological chain partners actively participated in this tour, including Synopsys, Imperas, Lauterbach, IAR, Silxin, etc.

Partner booths at the SiFive roadshow

In fact, the reason why RISC-V has grown explosively in just a few years is precisely because it far surpasses other competitors in terms of ecological construction. Although other competitors have done well enough, RISC-V is open source and open. , naturally attracts people who need PlanB. Because of this, the members of the RISC-V Foundation are growing rapidly every year.

At the Beijing Technology Forum, even though it rained that day, there were still too many people and the air conditioning was insufficient. Asanović apologized to the audience more than once. Of course, this once again confirmed the popularity of RISC-V.

RISC-V is inevitable

Asanović said in his speech that RISC-V has unlimited possibilities, so the evolution to an open source and open RISC-V architecture is inevitable. When recalling the architectures that disappeared in the past, he said that many architectures have come and gone, including IBM, SUN, MIPS and other companies, but they have not been able to continue their own architectures to this day on their own. Even Intel has failed to defeat Itanium and other companies. Innovation architecture.

The only active instruction sets today are X86, Arm and the rising RISC-V.

Asanović believes that there is no good or bad distinction between open standards and closed standards. Open architecture has proven to be successful in many fields, including networks, compilers, databases, graphics and today's instruction set battles, etc., but with At the same time, closed standards are also in these areas.

Asanović said that the reason why Berkeley created RISC-V in 2010 was mainly because a 64-bit instruction set architecture was needed for research at that time. Intel's X86 was closed, and Arm did not have a 64-bit architecture at the time (the 64-bit V8 architecture was launched in 2011 , not only can it be said that RISC-V is an opponent cultivated by Arm itself).

After the instruction set was frozen in 2014, RISC-V began to rush forward. In order to quickly expand the commercialization process of RISC-V, on the one hand, several founders established SiFive in 2015 to accelerate commercialization. On the other hand, they established the RISC-V Foundation in the same year to be fully responsible for the ecological construction of RISC-V.

Today, the RISC-V Foundation has gathered hundreds of companies, and SiFive has also received investment from industry partners including Qualcomm, Intel, Western Digital, and SK Hynix, and such as Intel's IFS (design foundry services) , also clearly pointed out the need for special support for RISC-V.

Asanović pointed out that the current RISC-V ecosystem is becoming increasingly complete. In terms of cores, there are open source cores, commercial cores, and independent cores. In terms of chips, there are also many successfully commercialized products.

In addition, Asanović also highlighted RISC-V’s software efforts.

Citing data, Asanović said that RISC-V is expected to grow to 80 billion cores in 2025, but he still believes that this number is slightly conservative. He took Qinheng's RISC-V MCU CH32V003 as an example. The product sells for less than US$0.1 per unit. Its full cost-effectiveness proves that RISC-V has an unlimited future.

Android has regarded RISC-V as a first-level platform (Tier1), on par with Arm. In addition, SiFive chief architect and Google's TPU chip architect also demonstrated their cooperation plan at the AI ​​Hardware Summit in September 2022. In addition, RISC-V has also become a Tier-1 architecture supported by Debian.

In other aspects such as compilers, middleware, development boards, EDA tools, etc., the expansion speed of RISC-V is also amazing.

As SiFive employee No. 6, Gang Zhijian said that when he first joined SiFive, even though the company was still relatively small, the development goals of RISC-V were indeed the same as previously preset, but the speed was faster than imagined.

RISC-V collaboration on software ecosystem

Fragmentation and Diversification

Asanović used two diagrams to explain the difference between fragmentation and diversification, where fragmentation refers to solving the same problem in different ways, and diversification refers to solving different problems in different ways. Asanović emphasized that if a company is still developing its own instruction set today, it is 100% a mistake. The main reason is that no company can have complete capabilities to engage in all software development.

Currently, RISC-V is avoiding fragmentation, including a unified instruction set, and a unified software platform.

A standardized, community-driven ecosystem should be the best practice. SiFive recently donated its WorldGuard security solution to RISC-V International to further help standardize the ecosystem and ensure the highest security level for RISC-V products. "If it is not included in the standard, you will have to write various software yourself, which will lead to fragmentation." Gang Zhijian said.

The current state of the SoC instruction set is very fragmented. For example, applications, GPU, graphics, RF DSP, audio DSP, security and power supply are all using different IPs. It becomes difficult to adapt software or firmware to different processors. More and more complex.

RISC-V does not experience fragmentation due to its unified instruction set. Gang Zhijian even said that although Arm has a unified architecture, if you consider different instruction sets such as V7, V8, and V9, as well as different processors such as 32-bit and 64-bit, it is the birthplace of the largest fragmentation.

It is precisely because of the flexibility of RISC-V that it can give full play to its diversified value. For example, in the field of AI, a year ago, most people did not know about generative AI or Transformer. However, in just half a year, The demand for large models increased dramatically. AI is changing so fast. In order to adapt to this rapid change, hardware also needs to iterate quickly, and RISC-V's unique programmable environment makes it easy to accelerator.

Asanović gave an example that instruction sets of different eras represent different technologies. IBM360 represents the transistor era, X86 represents the microprocessor era, Arm represents the mobile era, and RISC-V represents the vertical semiconductor era. More system companies can build their own chips through RISC-V and customize them according to actual products and applications to develop the most reasonable chips. This is exactly what the diversified nature gives you.

Another good news is that recently, 13 companies including Samsung, Intel, and Qualcomm launched the RISC-V software ecosystem plan RISE to promote the marketization of RISC-V processors in fields such as mobile communications, data centers, edge computing, and autonomous driving. This is also a highlight of RISC-V in terms of diversification.

RISC-V is no longer just low-end

As mentioned above, RISC-V is challenging Arm in multiple areas.

Gang Zhijian also said frankly, "Previously, when people saw RISC-V, they only saw it as a small CPU or MCU, most of which were used in embedded applications. This will cause misunderstanding to many people, that is, RISC-V It can only make low-end products, but RISC-V has no restrictions. Not only SiFive, other companies are also making high-performance RISC-V.”

In Gang Zhijian’s speech, SiFive’s product and technology roadmap was introduced in detail. Currently, SiFive can be divided into two parts: 32/64-bit compatible products and 64-bit high-performance products, which include four major product lines for automotive, artificial intelligence, high-performance and essential.

SiFive product line overview

The SiFive Essential series offers the freedom to choose to use standard predefined cores or build your own processor configuration using SiFive Core Designer. SiFive Performance processors deliver unparalleled performance in an energy-efficient small form factor, while the SiFive Intelligence Series adopts a software-first approach to processor design to meet the future needs of deploying machine learning technology into edge computing and features High-performance vector computing capabilities. SiFive Automotive solutions provide high-end application and real-time processors with industry-leading performance and the lowest area and power consumption, tailored for the specific needs of vehicles such as safety and performance.

Especially for the automotive sector, Gangzhi strongly emphasized that automotive electronics are being upgraded very quickly. Both RISC-V and Arm are almost at the same level, which gives RISC-V a great opportunity. In fact, according to the indicators published by SiFive, its PPA is no less than Arm.