Typical architecture of vehicle-mounted SOC computing chip

The following figure shows the typical architecture of an in-vehicle AI chip. According to the different computing types and tasks undertaken, the main computing modules are divided into two categories: CPU and NPU. Generally speaking, the CPU performs general logic calculations, and the NPU is suitable for A1 calculations for environmental perception.

The main computing modules include:

(1)CPU

In addition to performing calculations related to AI processing, the vehicle system still has certain computing requirements to ensure the implementation of various system applications. This part of the computing power is provided by the CPU subsystem. The computing requirements supported by the CPU subsystem include: sensor fusion, pre- and post-processing, attribute reconstruction, odometer positioning matching, vehicle control, traditional algorithm element calculation, scheduling and computing tasks, perception information output, etc.

To meet the computing requirements of the above-mentioned intelligent driving scenarios, the CPU subsystem usually adopts a cluster design based on ARM Cortex-A. The Cortex-A series is a low-power core that adopts the ARMv8/ARMv9 instruction set. It can achieve low power consumption characteristics while improving performance to meet the needs of high-energy-efficiency computing scenarios. Compared with the previous generation of ARM processors, it adopts enhanced computing performance: enhanced NEON technology can accelerate multimedia and signal processing algorithms, such as video encoding/decoding, 2D/3D graphics, audio and voice processing, and image processing. Double-precision floating-point SIMD significantly improves the support efficiency for a wider range of algorithms. While improving performance, it can still maintain low energy consumption characteristics. Different cores in the CPU cluster can be divided into different voltage domains and power gated in groups, meeting the needs of different computing scenarios while achieving low power consumption characteristics. The cluster design has good flexibility, scalability, security, and high energy efficiency, and can fully adapt to the computing needs of complex scenarios such as ADAS/cockpit/intelligent human-computer interaction.

(2)NPU

The intelligent connected vehicle field includes scenarios such as advanced driver assistance, autonomous driving, human-computer interaction, and infotainment. The computing power requirements are high and the degree of parallelism is high. It requires a powerful and energy-efficient on-board computing chip as a computing infrastructure to complete the computing processing, self-learning, and autonomous evolution of vision, speech, and NLP. Applying deep learning to the above typical scenarios to design dedicated on-board computing chips, combined with engineering technology to achieve implementation, will lead the rapid development of the industry.

Combine advanced algorithms and advanced processor architecture design to ultimately achieve the optimal solution in terms of power consumption, performance (including speed and accuracy), and energy efficiency. NPU is a dedicated processor for artificial intelligence computing scenarios. It uses the rapid evolution of deep learning technology to learn from data through algorithms, combines innovation in chip architecture, and combines the computing characteristics of autonomous driving vertical scenarios. It is dedicated to performing artificial intelligence parallel computing. It is a typical heterogeneous multi-instruction multi-data system. It is specially optimized for memory architecture design, which enables data to be transferred freely, performs multiple calculations, and allows different components to operate simultaneously, improving the efficiency of Al operations. NPU provides sufficient computing power without sacrificing accuracy. It has the characteristics of high performance, low power consumption, and low cost.

In addition, this type of chip needs to reflect a certain degree of scenario versatility. The processor has designed combination, gating and other logical structures for computing modules such as MAC units, making it flexible and configurable, and can be tightly coupled with the application development tool chain; it supports the calculation of models obtained from multiple training frameworks such as MXNet, Caffe, Tensorflow. PyTorch, supports the calculation of multiple deep learning algorithms such as traditional convolution calculation, circular convolution calculation, and fully connected calculation, supports the calculation of models with different parameter scales, and can be configured as floating-point and fixed-point calculations of different precisions through the compiler, supports heterogeneous computing, and can work with the CPU to complete the calculation of heterogeneous models to improve overall performance. The design characteristics of the NPU itself and its close integration with the tool chain determine its high flexibility and strong versatility, which can adapt to the computing needs of different scenarios.

As innovative applications such as autonomous driving are developed based on massive data analysis, applications such as environmental perception and object recognition required by autonomous driving require extremely fast computing responses, usually using deep neural network algorithms. While ensuring fast performance and high efficiency, power consumption cannot be too high, and cannot have a significant impact on the range of autonomous vehicles. Higher requirements are placed on the efficiency of computing chips, and the computing chip architecture continues to develop, extending from general computing to dedicated computing. The current mainstream autonomous driving computing chips can be divided into several categories such as GPU, ASIC, FPGA, DSP, etc. in processing deep learning AI algorithms. Choosing the best solution is usually related to multiple factors, such as application scenarios, chip specifications (including hardware interfaces, power consumption, etc.), design constraints, software tool chains, and time to market rhythm.

In the era of smart cars, Al computing chips are digital engines, and computing power is the most important hardware cornerstone for smart cars. Currently, insufficient computing power has become the core bottleneck in the development of smart cars. The continuous improvement of computing power is a sign of the progress of automotive intelligence. For each additional level of autonomous driving, the computing power requirement increases tenfold. For each level of autonomous driving, the required chip computing power will increase by an order of magnitude.

In the future, multi-core CPUs, GPUs, DSPs, and NPUs will develop towards SOC through integration and combination driven by the market and demand. Modular design of software and hardware, adoption of differentiated chip solutions, and connection of upstream and downstream industries through heterogeneous general platforms, buses, and various peripheral controllers will be adopted. Safe, stable, scalable, and customizable systems will be adopted to decouple different software and hardware life cycles and development processes, and large-scale autonomous driving will be achieved through standardization.

The four major trends in E/E architecture change: computing centralization, software and hardware decoupling, platform standardization, and function customization. High-performance hardware is embedded as an investment, and software update services are used as profit points. This also puts forward the demand for in-vehicle AI computing chips.