How to use special graphics in MAX+PLUSⅡ symbol library

MAX+PLUSⅡ symbol library provides many basic primitives (also called primitives) for graphic design files to call. These primitives can be roughly divided into several categories, such as buffers, registers, input and output ports, and logic gate primitives. Among them, the use of registers and combinational logic gates is relatively simple. Here is a brief introduction to the use of other special primitives.

1) Buffer primitives
The buffer primitives provided in the .gdf file include CARRY (carry buffer), CASCADE (cascade buffer), EXP (logic extension buffer), LCELL (logic cell buffer), MECLL (macrocell buffer), GLOBAL (global buffer), SCLK (synchronous clock buffer), SOFT (soft buffer), TRI (tri-state buffer), OPNDRN and WIRE. All primitives can be found in the Prim library. Except for TRI, OPNDRN and WIRE, other buffer primitives can control the logic synthesis process. In most cases, these primitives do not need to be used. However, if the compiler prompts that the design is too complex to handle, the user needs to insert some of the above primitives into the design to guide the logic synthesizer to produce the desired results.

(1) CARRY
CARRY can set the carry output logic for one logic block and serve as the carry input for another logic block. This primitive can be used to implement fast carry chain logic in adders and counters. A CARRY can feed one or two logic cones.
If a CARRY feeds two logic cones at the same time, then one and only one of the logic cones must be buffered by the other CARRY. In this case, the two logic cones are implemented in the same logic cell (LC). For the first stage of adders and counters, this rule must be followed to connect the addition and carry output logic together. The
logic cone whose output is connected to the CARRY can have at most two inputs, and the third input can only come from the CARRY input.
The output of the CARRY cannot be sent to the OUTPUT or OUTPUTC pins. Two CARRYs cannot output to the same gate. CARRY cannot use the INPUT or INPUTC pins as input, nor can it use registers as input.

(2) CASCADE
CASCADE can be used as the cascade output of an AND gate logic or an OR logic, or as the cascade input of another AND logic or OR logic. The cascade input function can be used to OR or AND the fast cascade output of a combinational logic with the output of another adjacent combinational logic in the device.
A CASCADE can only output to one gate and can only get cascade input from one gate, and these gates can only be "AND gates" or "OR gates", such as AND, NAND, BAND, BNAND, OR, NOR, BOR and BNOR.
CASCADE cannot output to an "exclusive OR gate" (XOR), nor can it output to a register, and even less to the OUTPUT or OUTPUTC pins. De Morgan's inversion theorem requires that the types of "AND gates" or "OR gates" cascaded in a cascade chain must be the same. A cascaded "AND gate" cannot output to a cascaded "OR gate", and vice versa. Two CASCADEs cannot output to the same gate.
During the logic synthesis process, you can let the compiler automatically insert or delete CASCADE. The specific method is to control the logic synthesis by making different settings for the Cascade Chain logic option, or to select the Cascade Chain in the logic synthesis option.

(3) EXP
EXP indicates that an extended product term is required in the design. The extended product term is inverted in the device. Whether to use the extended product term depends on the target logic polarity. For example, if an EXP is to be output to two AND gates, and the second AND gate has an inverting input, then during logic synthesis, the EXP output to the inverting input is deleted and a positive logic is generated. The EXP output to the non-inverting input is not deleted, but is used to implement the target logic. (Generally, the logic synthesizer should decide where to insert or delete the EXP.)
In a device containing multiple LABs, an EXP can only output to logic in the same LAB. If an EXP is to output to logic in different LABs, an EXP must be copied for each LAB. If a design contains a large number of EXPs, the logic synthesizer may convert them to LCELLs in order to balance the use of product terms and logic cells.

(4) GLOBAL
GLOBAL indicates that a signal must use a global (synchronous) clock, clear, preset or output enable signal instead of being generated by internal logic or driven by a general I/O pin. The use of global signals varies depending on the global signals available in various series of devices.
If an input pin is directly connected to the input of GLOBAL, then the output of GLOBAL can be used as the clock, clear, preset or output enable input signal of another primitive. In this case, the output of GLOBAL must be directly connected to the input of a register or TRI. If the output of GLOBAL is connected to the output enable of TRI, it may be necessary to add a NOT gate between the input pin and GLOBAL.
Global signals are much faster than local signals (array signals) and will save device resources for other logic. GLOBAL is often used to provide a global clock for the entire design or part of the design. To check whether the clock used by the register is the global clock, you can view the report file.
Another way to use GLOBAL is to use the Logic Synthesis command to instruct the compiler to automatically select an existing signal in the design as a global clock, clear, preset, or output enable signal. To do this, select the menu command Assign / Global Project Logic Synthesis, and select the corresponding option in the Automatic Global column in the dialog box that appears.

(5) SOFT
SOFT is used to indicate that a logic unit may be required in the design. During the design processing, the logic synthesizer checks the input logic of the SOFT to determine whether a logic unit is required. If required, the SOFT is converted to LCELL. If not, the SOFT is deleted. This explains the role of SOFT in logic synthesis. When compiling this design project, the logic synthesizer will delete the SOFT, and after synthesis, the design will only occupy one logic unit.
If the compiler prompts that a design is too complex, you can insert a SOFT in the design to prohibit logic expansion. For example, you can add a SOFT after a functional module to isolate two combinational logic circuits. If you select the menu command Assign / Global Project Logic Synthesis, then click the Define Synthesis Style...>> button in the dialog box that appears, and then click Advanced Options... in the dialog box that opens, and select the SOFT Buffer Insertion item in the dialog box shown in Figure 5.70 of the book, then when compiling, the compiler will automatically insert a SOFT in the design.

(6) LCELL
LCELL allocates a logic cell (LC) to the logic design. LCELL generates a positive logic and a negative logic that are valid in all logics in the entire device. MCELL has the same function as LCELL and is applicable to the early version of MAX+PLUSⅡ. LCELL should be used when designing with the new version of MAX+PLUSⅡ. One LCELL generally occupies one logic cell and will not be deleted during the logic synthesis process. However, do not use LCELL to generate the required delay or asynchronous pulse. Because the delay generated in this way varies with temperature, power supply voltage and the manufacturing process of the device used, it will cause race conditions and thus produce an unreliable circuit.
If you select the menu command Processing / Design Doctor Setting... in the compiler window, and then click the Advanced Options>> button in the setting dialog box that appears, and then open the Delay Chain option in Design Doctor shown in Figure 5.71 of the book, then when compiling, the compiler will issue a warning message for the series LCELL or EXP used to generate delay or asynchronous pulses.

(7) TRI
TRI is a three-state buffer with input, output, and a high-level active output enable signal. If the output enable of TRI is connected to VCC or a logic function block whose final result is always true, then TRI may be converted to SOFT during logic synthesis.
A TRI can only drive one BIDIR or BIDIRC pin. If there is feedback at the TRI output, a BIDIR or BIDIRC pin must be used. If a TRI outputs to a logic block, it must also output to a BIDIR or BIDIRC pin. However, if it is output to the BIDIR or BIDIRC pin, it does not need to output to other outputs. When the output enable signal is not connected to VCC, the output of TRI must be connected to the OUTPUT, OUTPUTC, BIDIR, or BIDIRC pins because the internal signal cannot be tri-stated.

(8) OPNDRN
OPNDRN is similar to TRI, with one input port and one output port. When OPNDRN is fed by a signal called "in", it is equivalent to the input terminal of TRI being grounded (GND), and the output enable terminal being connected to the inverted phase of "in".
If the input of OPNDRN is low, the output is low; if the input is high, the output is high impedance. OPNDRN is supported by specific device families (such as FLEX 10K, MAX7000S, etc.). In other device families, it will be converted to TRI. If you select the menu command Assign/ Global Project Logic Synthesis..., and turn on the Automatic Open[CD*2]Drain Pins item in the dialog box that appears, the compiler will automatically convert the following two structures into OPNDRN during compilation.

Structure 1: The output enable terminal of TRI is connected to any signal, but the input terminal is grounded (GND);
Structure 2: The signal connected to the output enable terminal of TRI is the inversion of its input signal.
One OPNDRN can only drive one BIDIR or BIDIRC pin. If there is a feedback loop after the OPNDRN, the BIDIR or BIDIRC pin must be used. If an OPNDRN has a logic input, it must also be output to the BIDIR or BIDIRC pin. If the OPNDRN outputs to a BIDIR or BIDIRC pin, it can no longer drive any other output.

(9) WIRE
WIRE is used to rename nodes or buses. It does not implement any logical functions. WIRE is directional. For example, a WIRE can be used to rename the input or output part of a bidirectional bus.