Series Inductance--How Connectors Generate Electromagnetic Interference

Electromagnetic interference is caused by signal current in a large loop.

Figure 9.6 illustrates a common electromagnetic interference problem. A 64-bit bus is connected from card A to the motherboard through connector B. The motherboard may be a main CPU card or a passive channel to other daughter cards. The return current of the 64 signal lines flows from motherboard C back to card A, and most of it passes through the ground pin of connector B.

Only a small portion of the signal return current flows back to card A via a different path. However, it is this small portion of return current that causes a lot of EMI problems.

When high-frequency current flows through a large loop, it will radiate a large amount of electromagnetic energy, which will not pass the radiation test specified by the FCC or VDE. The main task of EMI design is to minimize the cross-sectional area of ​​the current loop of all signals. For example, on a complete ground plane, high-frequency current tends to return just below the trace. A 6IN long trace 0.010IN away from the ground plane has a loop area of ​​only 0.006IN to the power of 2. Such a large loop area is acceptable in terms of EMI. In Figure 9.6, the 64-bit bus signal on boards A and C is returned by the complete ground plane, so we can ignore the loop area between the signal and the ground.

Any blockage or discontinuity in the return current path, such as a transition on a connector ground pin, will create "bubbles" in the current loop. Whether these bubbles are large enough to cause excessive emissions depends on the total DI/DT value of the signal current in the loop.

In Figure 9.6, the bubble in the loop area generally occurs in connector B because the signal and ground pins on the connector are separated. This bubble is marked as G1, and most of the loop inductance of the 64-bit bus signal path comes from the inductance of loop G1.

Whether the signal return current has an alternative return path depends on the physical structure of connector B and the specifics of the chassis structure in which boards A and C are located. Any current returning to the source on board A without passing through connector B will contain a large loop area and generate a large amount of radiation.

For example, in Figure 9.7, assume that boards A and C share two connectors, and the additional connector is marked as D, which is arranged at a distance from connector B. Now part of the signal return current can flow from the ground wire on connector D to A, as shown in loop G2 in Figure 9.7.

Adjusting the ratio of the signal return current through connector D depends on the ratio of the inductance of loop G1 (see Figure 9.6) to the inductance of G2 (see Figure 9.7):

(Formula 5)

At very low frequencies, the amount of signal return current flowing through connector D depends on the ratio of the impedances, while at higher frequencies, it depends on the ratio of the inductances in the above equation. Since EMI is a high-frequency problem, we are only concerned with the ratio of the two loop inductances here.

Because loop G1 is smaller in area and its inductance is smaller than G2, only a small portion of the return signal current passes through path G2. However, even such a small portion of the current is enough to cause the radiation to exceed the standard. Above 30MHZ, tested at a distance of 3M from the device, the radiation limits of FCC and VDE are roughly 100UV/M. For more details on radiation standards and design techniques to prevent electromagnetic radiation, please refer to the works of OTT, MARDIGUIAN and KEISER.

It is unrealistic to accurately calculate the radiation intensity level of a digital product because there are too many factors that affect the result. The following formula represents a simple constraint: an open measurement test occasion, above 30MHZ, and the loop area, peak current and rise time that meet the FCC and VDE radiation limits.

(Formula 6)

Where: E = national radiation electric field strength at 3M, V/MA
= radiation loop area, IN2IP
= peak current, A
T10~90% = signal rise time
FCKOCK = time frequency, HZ

Note about the above formula:

It is common for the radiation index of the final product to differ by 20DB from the index estimated by the above formula, which includes a large correction factor.

It should be clear that the radiation test is the sum of the radiation of all lines in the test system. If one line just meets the standard, then adding 100 lines will definitely not meet the standard.

Before finalizing the design, building a simulated system to test it, which only includes some clock signals passing through the connector system, may sound wasteful, but it will save a lot of money in the end. Because when the mechanical packaging and shielding need to be redesigned at the end of the project, the cost will increase dramatically.

Example: Noise radiation from a connector

Figure 9.8 shows a typical 16-bit bus. Let's calculate the inductance of paths G1 and G2, as well as the radiation of path G1 and the radiation of path G2 step by step.

Inductance of path G1:

(Formula 7)

R=0.025/2 (pin radius, half of the diameter, IN)
Note: We use H/R, not 2H/D)
W1=0.2 (distance from signal to ground, IN)
H=0.4 (connector pin length, IN)
1/2=correction factor, because there are ground wires on both sides of the signal pin (see Principle 2 in "Mutual Inductance-How Connectors Cause Crosstalk")

Inductance of path G2:

(Formula 8)

R = 0.025/2 (pin radius, half the diameter, IN)
W1 = 0.2 (distance from signal to connector D, IN)
H = 0.4 (connector pin length, IN)

Assuming that each drive signal propagates through a 50 ohm transmission line, the amplitude is a typical TTL level of 3.7V, and the peak-to-peak value of the signal current is 74MA. The peak current is half of that or plus or minus 37MA.

Use Equation 5 to extract the peak current of path Y:

(Formula 9)

Now use Equation 6 to estimate the radiation of loops G1 and G2. First calculate G1:

(Formula 10)

A=0.08 (pin length 0.4IN*signal to ground distance 0.2IN, IN to the power of 2)
IC1=0.037 (peak current, A)
T10~90%=5*10 to the power of -9 (signal rise time, S)
FCKOCK=100MHZ

The radiation of one signal line is 82UV. The total radiation is approximately proportional to the square root of the number of related signal lines. The radiation of all 16 lines is:

(Formula 11)

According to this design, this connector arrangement will not pass the specified test. Let's look at the situation of connector D:

(Formula 12)

A=2.4 (pin length 0.4IN/signal to ground distance 6IN, IN to the power of 2)
IG2=0.0015 (peak current, A)
T10~90%=5*10 to the power of -9 (signal rise time, S)
FCIOK=100MHZ

The radiation of one signal line is 90UV, and the total radiation of all 16 lines is:

(Formula 13)

In fact, loop G2 radiates more than G1 because the inductance LG2 increases only with the logarithmic value of the distance between connectors B and D, while the increase in the area of ​​loop G2 is directly proportional to the distance between connectors B and D. Although the increase in inductance reduces the current flowing through G2, the increase in the loop area leads to a much greater increase in radiation. Increasing the distance between connectors B and D actually makes the radiation problem worse.

Here are some guidelines for effectively reducing connector radiation:

Guideline 1: Use more ground pins in connector B and make the ground line close to each signal line, thereby effectively reducing the effective radiation loop area in connector B.

Rule 2 Adding more ground wires in connector B can also reduce its inductance. From Equation 5, we can see that this can reduce the current flowing in the far-end loop.

Rule 3: Place all motherboard connectors on card A close together to break or eliminate far-end return current paths.

Rule 4: Place continuous ground points along the edges of Board A and Board C. This provides a very low impedance return path according to Equation 5, reducing far-end loop current.

Guideline 5: Do not connect the I/O cable to the outer edge of card A, as this will create a large far return current path from the motherboard C, through the ground and the I/O cable back to card A. The cable should be edged on the motherboard, or high-frequency filtering should be performed on the motherboard near connector B.

Rule 6 For the driver gate circuit used, the rise time should be as long as possible. Equation 6 shows that the radiation is proportional to the inverse of the rise time.