Introduction of ADV202 Codec Chip

ADV202 is a single-chip IPEG2000 (ISO/IECl5444-1 image compression standard) codec chip recently launched by AD Corporation of the United States for video and high-bandwidth still image compression. It is the only chip on the market today that can compress and decompress standard (SD) video signals and high-definition (HDTV) video signals in real time. The patented space-efficient recursive filtering (SURF) technology enables it to have low-power and low-cost wavelet compression. The dedicated video interface it provides can be seamlessly connected to digital video interfaces such as ITU.R-BT656, SMPTE125M, SMPTE293M [525p], and the flexible asynchronous SRAM-style host interface allows seamless connection to most 16/32-bit microcontrollers and ASIC devices.

The internal functional block diagram of ADV202 is shown in Figure 1. After the input video or image data enters the video interface, it is deinterlaced and transmitted to the wavelet transform engine. In the wavelet engine, each frame of the image or each block is decomposed into many sub-bands through a 5/3 or 9/7 filter, and the generated wavelet coefficients are written into the internal register. The entropy encoder encodes the image data into data that conforms to the JPEG2000 standard. The internal DMA engine provides high-bandwidth transmission between memories and high-performance transmission between modules and memories. The internal FIFO provides storage space for pixel data, code stream data, feature data, and auxiliary data, which can be directly accessed by an external host through a standard address read and write cycle, or can be accessed through DMA or a dedicated hardware handshake mechanism using the DREQ/DACK protocol. The host interface provides a 16/32-bit control bus and an 8/16/32-bit data transmission bus for the configuration, control and status transfer of internal registers and the transmission of compressed data streams.