PCell caching technology based on OPENACCESS

In computer programs, we use caching techniques to store the results of frequently used functions on disk, so when we execute repeated instructions, we don't have to repeat them and get the results faster. The same technology can also be used to speed up the display of parameterized cells (PCells) in custom IC designs. Some electronic design automation (EDA) tools automatically cache PCells to improve performance; some require additional licensing; and others do not provide fast access capabilities at all. In addition to the performance benefits, PCell caching technology also allows other tools in the design flow to read and use tool-specific PCells.

PCells are used in the design of analog and custom digital circuits. They are software scripts used to define the physical layout in custom IC layout tools based on a set of variable parameters (Figure 1). PCells are the building blocks of custom design, providing a single programmable PCell to replace many different versions of hand-drawn cells. PCells can automate very complex functions, maintain intricate relationships, and even interact with the environment.

When a layout containing PCells is opened for viewing using the Layout Editor, the tool runs the individual PCell scripts, generates the corresponding layout and saves it in memory. If any parameters are changed – either manually or in the parameter property sheet – the Layout Editor must re-assign the PCells and change the layout appropriately. In many tools, only the PCell handlers and handler-specific parameters are written to disk when the layout is saved or closed, forcing the tool to re-assign the PCells each time it is opened.

Caching is used to write the assigned PCell layout to disk so that the layout content generated by the source tool can be read. Without caching, the PCell layout content will not be visible when opened with other tools unless the other tools can also execute PCell scripts.

Patented scripting language, an evolving standard

Historically, PCells have been written in proprietary scripting languages ​​(e.g., Cadence® SKILL®) developed for individual proprietary layout tools. This has resulted in most existing PCells being invisible to other vendors’ tools because those other tools do not have the software required to run the proprietary script assignments.

This has now changed, thanks to the efforts of the Interoperable PDK Library (IPL) Alliance, which has initiated a standard that will allow all vendors to implement interoperable PCells (see www.IPLnow.com). The PCells used in the IPL Alliance standard are written in the interoperable Python scripting language and are called PyCells™ by their developer Ciranova.

Now you can finally create PCells that can be opened and modified by almost any EDA tool.

Interoperable databases make the PCELL cache dream come true

All EDA tools are built on basic databases that perform a bridge function to store and retrieve semiconductor design data in a converged manner. Until recently, EDA tools have been built on proprietary databases. If an EDA tool uses a proprietary database, the only way other tools can "see" the layout is that it must be converted to a common semiconductor design format such as GDSII. During the conversion process, the original tool evaluates the PCells and their parameters, and then rewrites the physical layout into a GDSII format geometry, discarding many of the content and parameters associated with the PCell.

Once converted to GDSII, in most cases the original tool cannot recognize the layout data. Therefore, for PCells, the GDSII format conversion is irreversible. If the user wants to view or modify his PCells with a proprietary database-based tool, he must pay a licensing fee to the tool supplier every year during the design life cycle. This is the "tool tax", and no user is willing to pay it.

In recent years, the interoperable database standard OPENACCESS (OA) developed by Silicon Integration Initiative (Si2) has led to the trend of using multiple tools in semiconductor custom IC design. This database allows all tools to read and write the same database, and also provides different tools to operate on the same memory data in real time.

Any other tool that complies with the OA specification can see the PCells cached in the OpenAccess database. Almost all major layout editors and most custom design tools in the EDA industry can - or will soon be able to - at least read and write to the OA database. But what if another vendor tool modifies the cached proprietary PCell?

The OA database is also the basis of PyCells, which can be used by any OA-based tool through the PyCellAPI, without the need for caching to be "seen" by other tools. PyCells is fully interoperable when using the IPL-standard Interoperable Component Description Format (iCDF) and Tcl callbacks in IPL-compliant tools.

PCELL cache objects and how they work

The compiled PCell code is ready for use by custom IC design tools and is called a PCell "supermaster". Supermasters do not contain parameter values ​​during evaluation; during assignment, only variables are provided by the current tool using the Component Description Format (CDF) - or Interoperable CDF (iCDF) file.

When you manually place or instantiate a PCell into a layout, the tool reads the default parameters from the CDF file and creates a dedicated instantiation version of the cell in memory. This version is called a PCell "submaster". All default parameters, or parameters that have been modified, are stored as the contents of a dedicated submaster. When you assign values ​​to a PCell, the layout editor evaluates the submasters using these dedicated parameters, writes the layout to memory, and presents it in the layout editor for viewing or editing. The next time you open the layout, the PCells will have to be reassigned to create a new layout. Imagine that in a layout with thousands of PCells, this must take a lot of time.

However, if the tool stores submasters to disk (cache), then there is no need to re-assign them every time, which can greatly speed up the layout drawing time. In addition, each time a submaster is created, before assigning PCell, the tool will check whether the cache contains the same submaster, and then create a new layout. Even if the same PCell with the same parameters has been used thousands of times (such as Contact), only one version of the layout needs to be saved in the cache, saving more time and disk space.

PCELLS-based caching technology enables interoperability

Caching is very useful in multi-tool design environments, or during transitions to newer tools, when there are no interoperable PCells available, or when there is a large, existing library of PCells available. There are two main options in this area:

Express PCells: Many of today's PCells are written in Cadence's proprietary SKILL scripting language. Even for use in newer Cadence OA versions, SKILL PCells are not necessarily visible to other tools because they are not automatically cached. To make them "visible" to other tools, Cadence Express PCells can be used to cache cells in the OA database. This makes the cells visible to other non-Cadence tools in a read-only manner.

In some tools, you can see the property sheet for program-specific parameters, but you cannot modify PCells in other tools unless you process them into a simple layout first. In addition, stretchhandles and auto-abutment callbacks are not visible in other tools. (For more information on PCell functionality, see the article ASilicon-provenInteroperablePDK in the Technology section of the SpringSoft website.)

For example, for users of non-Cadence DRC tools, Express PCells is required to be able to perform DRC directly from OA. In a multi-tool design flow, different layout modules are completed by different layout editors. Express PCells is a viable solution for combining these different modules. Of course, to further modify the Cadence-based modules, these modules need to be replaced completely, or at least the PCell instance needs to be modified. This is no different from a typical SOC flow (in which different modules are designed by different teams or even different companies).

PCellXtreme: Ciranova's PCellXtreme™ also works with the Cadence environment, just like ExpressPCells caches SKILLPCells, which can speed up the time to open the layout. However, unlike ExpressPCells, the PCellXtreme service can read and modify PCell parameters in addition to seeing the cached PCell. PCellXtreme does not convert PCell code or assign values; if there is no second tool to read the PCell parameters, PCellXtreme will generate a layout based on Cadence's SKILLPCell and put it in the cache. So the new layout is visible and refreshed in real time. Therefore, parameters modified by other tools can be recognized by all tools. This method requires the user to have at least one set of authorized Cadence tools in order to assign SKILLPCells.

However, it is important to note that PCellXtreme does not implement callbacks. Callbacks are a key element of many PCell parameters because they are used to calculate relative values, out of bounds values, etc. from the input parameters. Therefore, simply passing parameters is not enough. To implement callback functionality in non-Cadence tools, interoperable callback functionality that is exactly the same as the TCL callback defined in IPLAllianceReferenceflow1.0 must be available for other tools to use. For the Cadence environment, including clients operating PCells running in the IPL library, dual callbacks are required, so it is worth looking forward to more interoperable environments for TCL callbacks. With the proper settings of these two callbacks, interoperability of all parameters can be achieved.

Because stretchhandles and auto-abutments are OA content cached with the layout, users can write equivalent stretchhandle and auto-abutment programs in TCL or other interoperable scripting languages ​​to match SKILL functionality. Moving a stretchhandle causes the layout editor to update related parameters and trigger related callbacks. Parameter changes cause PCellXtreme to generate and cache the modified layout, just like the manually entered parameter changes mentioned above. Auto-abutments are also implemented in the same way.

Summarize

PCell caching technology is a practical approach to reusing existing layout data in OPENACCESS-based tools, providing users with higher interoperability than GDSII conversion of parameterized cells.

While the most interoperable solution is to use IPLAlliance's interoperable PyCells, callbacks, CDFs, and stretchhandle/auto-abutment technologies, PCell caching is a viable approach for using legacy PCells in a new OA tool, a hybrid design environment, or simply for the purpose of accelerating existing tools.