The overall architecture of the Weisheng WS51F7030 series

虹芯侠客

The overall architecture of the Weisheng WS51F7030 series [Copy link]

Overall architecture

1.1 8051 Core

1.1.1 Introduction

The standard 8051 , or MCS-51, is a 12 -cycle 8051 CPU , while the WS51F7030 series chips use a single-cycle 8051 CPU , which is fully compatible with the MCS-51 instruction set.

1.1.2 Addressing mode

The core addressing modes of 8051 are: immediate addressing, direct addressing, indirect addressing, register addressing, relative addressing, indexed addressing and bit addressing.

1.1.2.1 Immediate Addressing

Immediate addressing is to directly give the operands involved in the operation in the instruction operands. The instructions are as follows:

MOV A, #60H (This instruction sends 60H directly to accumulator A )

1.1.2.2 Direct Addressing

The operand of a direct addressing instruction gives the address of the operand involved in the operation. Direct addressing can only be used for special function registers, internal data areas and bit address spaces, and special function registers and bit address spaces can only be accessed using direct addressing. Examples of instructions are as follows:

ANL 50H , #91H ( AND the number in unit 50H with 91H , and store the result in unit 50H , where 50H is the address of the internal RAM )

1.1.2.3 Indirect Addressing

Indirect addressing is indicated by adding the " @ " symbol before R0 or R1 . Assuming the data in R1 is 40H , and the data in the 40H unit of the internal data memory is 55H , the instruction is MOV A , @R1 (transfer data 55H to accumulator A )

1.1.2.4 Register Addressing

Register addressing operates on the numbers in the selected working registers R7-R0 , accumulator A , general register B , address register and carry C , where registers R7-R0 are represented by the lower 3 bits of the instruction code , and ACC , B , DPTR and carry C are implicit in the instruction code. Therefore, register addressing also includes an implicit addressing mode. The working register work area is determined by RS1 and RS0 of the status register PSW . The registers specified by the instruction operands all refer to the registers in the current work area.

INC R0 ( data in R0 + 1 is written back to R0 )

1.1.2.5 Relative Addressing

Relative addressing is to add the current value in the program counter PC to the number given in the second byte of the instruction, and the result is used as the transfer address of the transfer instruction. The transfer address is also called the transfer destination address, the current value in the PC becomes the base address, and the number given in the second byte of the instruction becomes the offset. Since the destination address is relative to the base address in the PC , this addressing method is called relative addressing. The offset is a signed number, and the range that can be represented is +127--128 . This addressing method is mainly used for transfer instructions.

JC $+50H (If the carry bit C is 0 , the content in the program counter PC does not change, that is, it does not transfer. If the carry bit C is 1 , the current value and base address in PC plus the offset 50H are used as the destination address of the transfer instruction)

1.1.2.6 Indexed Addressing

In the displacement addressing mode, the instruction operand specifies a displacement register that stores the displacement base. In displacement addressing, the offset is added to the displacement base value, and the result is used as the address of the operand. The displacement registers include the program counter PC and the address register DPTR .

MOVC A , @A+DPTR (indicates that accumulator A is the offset register, and its content is added to the content of the address register DPTR . The result is used as the address of the operand, and the number in the unit is taken out and sent to accumulator A )

1.1.2.7- bit addressing

Bit addressing refers to the addressing mode for bit operations on some internal RAM and special function registers that can perform bit operations. When performing bit operations, the carry bit C is used as the bit operation accumulator. The instruction operand directly gives the address of the bit, and then the bit is operated according to the operation code. MOV C , 20H (send the value of the bit operation register with address 20H to the carry bit C )

1.1.3 Register Description

1.1.3.1 Program Counter PC

The program counter PC register is 16 bits and is a register specifically used to control the execution order of instructions. It has no register address. After the microcontroller is powered on or reset, the PC value is 0 , and the microcontroller starts executing the program from address zero.

1.1.3.2 Accumulator ACC

The accumulator ACC is a commonly used special register. The instruction system uses A as the mnemonic of the accumulator. It is often used to store operands and results of arithmetic or logical operations.

1.1.3.3 General Register B

B needs to be used in conjunction with ACC in multiplication and division operations . The MUL AB instruction multiplies the 8 -bit unsigned number in ACC and B , and the low byte of the resulting 16 -bit product is stored in A , and the high byte is stored in B. The DIV AB instruction divides B by A , and the integer quotient is stored in A , and the remainder is stored in B. Register B can also be used as a general temporary register.

1.1.3.4 Stack Pointer SP

The stack pointer SP is an 8- bit special register. It indicates the location of the top of the stack in the internal RAM block. After the system is reset, SP is initialized to 07H , so that the stack actually starts from unit 08H . Considering that units 08H-1FH belong to working register groups 1-3 respectively , if these areas are used in program design, it is best to change SP to 80H or larger. In program debugging, stack overflow often occurs. In order to facilitate finding program faults, a register SPMAX that records the maximum stack is set , which can be read through the Debug interface, address 0x1A .

1.1.3.5 Data Pointer DPTR

Data pointer DPTR0/DPTR1 are two 16 -bit special registers. Their high-order byte registers are represented by DP0H/DP1H , and their low-order byte registers are represented by DP0L/DP1L . DPTR0/DPTR1 can be selected through DPS (PSW.1) . Each DPTR can be processed as a 16 -bit register or as two independent 8 -bit registers DP0H/DP1H and DP0L/DP1L .

1.1.3.6 Status Register PSW

The status register PSW is the status register of the CPU . When the CPU performs arithmetic or logical operations, the corresponding PSW status bits will change.