Design of Class AB Output Operational Amplifier in Audio Power Amplifier Chip

As we all know, Class AB audio amplifiers have higher efficiency than Class A (generally around 50%) and lower crossover distortion than Class B [1]. They are widely used in various mobile phones, MP3 and other portable devices and are the main force in the current audio amplifier market.

The output amplifier is the core part of the audio power amplifier chip, occupying most of its layout area. Its performance and integration directly affect the performance parameters and area size of the entire audio power amplifier chip.

In recent years, with the widespread application and continuous development of portable devices such as mobile phones, PDAs, MP3s, MP4s, etc., the requirements for audio power amplifier chips are getting higher and higher. High performance, low power consumption and high integration are the development direction . This is also the requirement for the output operational amplifier module.

Based on the N-well CMS process, this paper uses 0.6 μm DP-DM process to design an output power operational amplifier with low static power consumption, small input offset voltage, high gain, high common mode rejection ratio and power supply rejection ratio, large output swing, high bandwidth, and very small THD, which can be applied to most class AB audio amplifier chips.

2 Circuit Design

The entire circuit is divided into two stages. The first stage is a differential input circuit, and the second stage is a power tube push-pull output.

2.1 Selection of op amp structure

For the output power operational amplifier, the design focus is on the differential input circuit of the previous stage, hoping that it has the highest possible open-loop gain and unity gain frequency. At the same time, the performance limitations of speed, common-mode rejection ratio, power supply rejection ratio, power consumption, etc. must also be considered.

The differential circuit of the common source and common gate structure has a very high voltage gain, which is equivalent to the two-stage operational amplifier of the simple structure, and has better frequency characteristics. In the literature [2], three different structures of differential circuits are compared. The more common common source and common gate structures are the sleeve type and the folded type, as shown in Figure 1. Figure 1 (a) is a sleeve type common source and common gate differential operational amplifier. Its advantages are good frequency characteristics and low power consumption [2]. Its disadvantages are that there are too many "stacked" tubes on the branch, resulting in a smaller input common mode level range and output swing, which is not suitable for working under low voltage. Figure 1 (b) is a folded common source and common gate differential operational amplifier. Its frequency characteristics are equivalent to the sleeve type [2]. Compared with the sleeve type, its main advantage is that it has a larger input common mode level range, because it does not "stack" a common source and common gate tube on the upper end of the input tube, and a larger output swing. The disadvantage is that the input pair tube requires an external bias current, which consumes more power.

From the application point of view, among the above two op amp structures with similar voltage gain and frequency characteristics, the sleeve structure requires a higher supply voltage and has limitations in the input common-mode level range, making it unsuitable for use in the input stage circuit of the power amplifier. Although the folded common-source common-gate structure has greater power consumption, it is more suitable for the design requirements here. And the minimum supply voltage it requires is also within the acceptable range.

2.2 Bias circuit

The low-voltage cascode current mirror structure used in the bias circuit not only has the advantage of accurate current replication of ordinary cascode current mirrors, but also can operate at a lower power supply voltage than ordinary cascode current mirrors [3] as shown in Figure 2.

The minimum voltage margin consumed by the cascode current mirror M3-M4 of this structure is the sum of their overdrive voltages, and the input range of the Iref bias voltage Vb that can be accurately mirrored is:

2.3 Overall circuit

In the overall circuit of the op amp in Figure 3, Figure 3(a) is the main body of the op amp, including the differential input circuit and the push-pull output stage composed of power tubes Mp and Mn, and Figure 3(b) is its bias circuit, which provides bias voltages Vb1 to Vb8.

The differential input circuit is a folded common source and common gate structure. In the figure, M1 and M2 are input pairs, which are "+" and "+" input terminals respectively. M3 and M4 are the mirror parts of the low-voltage common source and common gate current mirror, providing tail current sources. Compared with Figure 1(b), the only difference is that the output end of the differential circuit, that is, M9, M10 and M15, M16 are inserted between M8 and M13, turning the single-ended output into a double-ended output, and controlling the gate voltage of the two power tubes Mp and Mn, so that Vgsp is slightly smaller than Vthp and Vgsn is slightly smaller than Vthn when the differential input is zero. Mp and Mn both work in the subthreshold region, and a certain current flows through. This is the basic feature of the AB class power amplifier, which eliminates crossover distortion as much as possible. In order to provide a large output current, their width-to-length ratio is very large (many identical tubes are connected in parallel on the layout, and the number of P tubes connected in parallel is about 3 times that of N tubes, so that the current flowing through the load in one cycle is equal)

In differential input, when the "+" terminal inputs a higher level, the current of the M2 branch decreases rapidly, and the currents flowing through the M5 and M7 branches remain equal, so the current flowing through M14 is less than the current flowing through M12, forcing M14 to work in the linear region. The voltage at point Y is very low. In order to keep the branch current unchanged, M13 enters the deep linear region, and VB drops sharply . At the same time, the currents of the M16 and M15 branches increase, and the currents of the M10 and M9 branches decrease, causing VA to decrease. Finally, VB drops to a very low level, VA follows VB to decrease, M10 and M9 are cut off, and M16 and M15 enter the linear region. At this time, Mn is cut off and Mp is turned on. Similarly, when the "-" terminal inputs a higher level, Mn is turned on and Mp is cut off. The output voltage swing is:

The low-frequency voltage gain of the op amp can be roughly calculated as follows:

AV1 is the gain of the first-stage differential circuit . M9, M10 and M15, M16 have little effect on the gain and can be ignored, so:

AV2 is the gain of the second-stage push-pull output stage:

The width-to-length ratio of the output power tube is adjusted to make Mp approximately 3 times of Mn, so that the above formula is valid.
For such a multi-pole two-stage op amp, Miller compensation is performed in series with the output resistor and capacitor to increase the phase margin and improve stability . Through frequency compensation, the two main poles are [1]:

Where RA is the total impedance from point A (or B) to ground, CA is the total parasitic capacitance from point A (or B) to ground, and Cι is the total capacitance at the output.

p1 is closest to the origin and is the pole generated by point A; p2 is the pole at the output end and is farther from the origin. At the same time, due to the formation of a path by the resistor and capacitor, a zero point is generated [1]:

Adjust R appropriately to make Z = p2, which cancels out the second main pole and increases the bandwidth.

2.4 Working Environment

It uses a single power supply and works in a closed loop state. The reference voltage is VDD/2 as shown in Figure 4. The closed loop transfer function is:

3 Simulation Results

The simulation performance parameters are shown in Table 1.

Figure 5 and Table 1 are simulation results, both measured under open-loop, no-load conditions The simulation tool is Cadence Spectre, using a 0.6 μm N-well CMOS process model, and the simulation environment is VDD = 5 V, T = 27 ° C, typical conditions The above results show that the unit gain bandwidth GB is 7.941 MHz, the phase margin is 74.60, and the frequency characteristics are good; the offset voltage is very small, 38.92 μV; there is a high voltage gain, common mode rejection ratio and power supply rejection ratio; in addition, when the input amplitude is 1 V and the frequency is 1 kHz, the output THD is very small, 0.004%

4 Conclusion

The class AB output power amplifier circuit designed in this paper adopts a folded common source and common gate structure, a power tube push-pull output, and uses an external current source for power supply. It uses a bias circuit with a low-voltage common source and common gate current mirror structure. The simulation structure shows that the op amp has the characteristics of high gain, low input offset voltage, low THD, etc., and has good frequency characteristics and low static power consumption, meeting the requirements of a high-performance class AB audio power amplifier chip. It can be seen that the design is almost satisfactory, and minor adjustments can also make each tube work in the most stable working area by changing the W/L ratio.