Use VCXO (voltage controlled crystal oscillator) as clock (CLK) generator

Structure and Application of VCXO CLK Generator

"VCXO", or voltage-controlled crystal oscillator, has an oscillation frequency determined by the crystal, but can be adjusted within a small range using a control voltage, typically 0V to 2V or 0V to 3V. The tuning range of a VCXO is ±100ppm to ±200ppm. Figure 1 shows the structure of a typical VCXO CLK generator and the crystal oscillator circuit model.


Figure 1. Structure of a typical VCXO CLK generator The

capacitance change of the varactor diodes CV1 and CV2 affects the crystal oscillator model, thereby changing the oscillation frequency. Two external parallel capacitors CS1 and CS2 are used to adjust the resonant range and center frequency offset. According to the crystal oscillator circuit shown in Figure 1, the resonant frequency can be expressed as follows:



Where CL is the equivalent load capacitance determined by CV1,2 and CS1,2. It can be accurately expressed as: CL = (CV1+CS1) || (CV2 + CS2). Taking the first-order approximation and considering that C1 << C0 and CL, the frequency increment of fC can be obtained.



Figure 2 shows a typical curve of fC changing with CS1 value when CS1 = CS2.


Figure 2. VCXO frequency vs. parallel capacitor CS1 (CS1=CS2)

Using this fine-tuning feature, a VCXO and PLL can be used to form a CLK generator with fine-tuning characteristics.

VCXO CLK has been used in many systems, such as digital TV, digital audio, ADSL, and STB. Maxim's MAX9485 is such a CLK generator chip, designed for MPEG-2 and Dolby Digital Audio (AC-3) applications [1]. It can provide almost all the frequencies used for digital audio to analog conversion, supporting sampling frequencies from 12kHz to 96kHz. Maxim has also designed a variety of VCXO CLK generators for other applications.

Key parameters of VCXO CLK generator

There are many parameters used to describe a VCXO CLK generator. The most important of these are the tuning voltage range, center frequency, pull range, and clock output jitter.

The tuning voltage range is the range over which the VCXO control voltage varies, which controls the capacitance of the varactor diode. It is typically 0V to 2V or 3V. The center frequency is the midpoint of the VCXO output frequency range. The pull range is the ratio of the frequency variation (increase or decrease) to the center frequency. This ratio is usually expressed in ppm (parts per million) and represents the relative frequency pull range of the VCXO. The pull range is typically around 100ppm to 200ppm, depending on the VCXO construction and the crystal selected.

Clock jitter is an important parameter of a CLK generator, and there are many definitions of jitter. The two most commonly used jitter parameters are called "period" jitter and "cycle-to-cycle" jitter, which we will discuss in detail in Section 4. Jitter depends on the construction of the CLK generator, and can vary from chip to chip, and different applications have different jitter requirements.

Crystal Selection and Board Design

The choice of crystal and PCB layout will have a certain impact on the performance parameters of the VCXO CLK generator. When selecting a crystal, in addition to frequency, package, accuracy and operating temperature range, the equivalent series resistance and load capacitance should also be considered in VCXO applications. The series resistance increases the power consumption of the crystal. The lower the resistance value, the easier it is for the oscillator to start. The load capacitance is an important parameter of the crystal. First, it determines the resonant frequency of the crystal. The nominal frequency of a general crystal refers to the resonant frequency after it is connected in parallel with the specified load capacitance. It should be noted that the nominal frequency here is the value calculated using formula (1) when CL is equal to the specified load capacitance, but not the calculated value 1/(2 π √L1C1). Therefore, the tuning range of the VCXO is closely related to the value of CL. When the load capacitance value is small, the tuning range of the VCXO is limited to the upper end; similarly, when the capacitance value is large, the tuning range will be limited to the lower end. The appropriate value of the load capacitance depends on the characteristics of the VCXO. For example, in the MAX9485 design, in order to balance the tuning range, the midpoint of the tuning curve, and simplify the board design, we chose a 27MHz crystal from Ecliptek (ECX-5527-27) [2] with a 14pf load capacitance. When using this crystal, the MAX9485 has a ±200ppm pulling range, as shown in Figure 3. It should be noted that the package will cause differences in the pulling range of the crystal. Generally, metal can packages have a larger pulling range than surface mount devices (SMD). However, a new SMD crystal produced by DAISHINKU Corp. [5] has recently achieved a pulling range similar to that of metal can crystals. We tested this SMD crystal (DSX530GA) and found that a ±200ppm frequency pulling range can be achieved when two 4pf shunt capacitors are connected externally, as shown in Figure 4.


Figure 3.


Figure 4.

To limit the tuning range of the VCXO, the upper adjustment range can be set by changing the external shunt capacitor. The shunt capacitor value ranges from 4ps to 7ps, depending on the board parasitic capacitance. On the other hand, the downward adjustment range depends on the internal varactor diode value and cannot be changed externally. In order to reduce the impact of parasitic capacitance on the upward frequency adjustment range, the parasitic capacitance between the crystal pin and the ground should be reduced as much as possible during the circuit board layout, and the pins should be kept clean from the ground layer and the power layer. For detailed circuit board layout, please refer to the MAX9485 evaluation kit [4].

Equipment for measuring output clock jitter

Jitter is an important performance parameter for oscillators. There are two most commonly used jitter definitions: period jitter and cycle-to-cycle jitter. See Figure 5 for details. To measure jitter, a high-speed digital oscilloscope can be used to sample a batch of data and calculate the jitter according to the definition. Tektronix oscilloscopes (TDS 7254) or Lecroy oscilloscopes (Wavepro 960) both provide such measurement software. We can also use a high-speed digital oscilloscope to measure period jitter in the time domain [3]. Figure 5 shows the setup. Cycle-to-cycle jitter cannot be measured in the time domain. However, if the jitter noise of each cycle is independent and evenly distributed, the cycle-to-cycle jitter is 1.414 times the period jitter. The MAX9485 can generate 21 different output frequencies, depending on the audio sampling frequency and the frequency scaling factor. We used the equipment shown in Figure 6 to measure the period jitter of various possible output clock frequencies. Table 1 shows the measurement results.


Figure 5. Output jitter measurement


Figure 6. Self-triggered jitter measurement setup

Table 1. Period jitter vs. output frequency

FOUT	Scaling Factor	F	JP (RMS)
(MHz)		(kHz)	(ps)	(UI)
73.728	768	96	twenty one	0.00155
67.7376	768	88.2	23.2	0.00157
49.152	768	64	42.6	0.00209
36.864	768	48	40	0.00147
36.864	384	96	37	0.00136
33.8688	768	44.1	44	0.00149
33.8688	384	88.2	41.3	0.00140
24.5760	768	32	66	0.00162
24.5760	384	64	92	0.00226
24.5760	256	96	50	0.00123
22.5792	256	88.2	55.1	0.00124
18.4320	384	48	59	0.00109
16.9344	384	44.1	69	0.00117
16.3840	256	64	134	0.00220
12.2880	256	48	84.8	0.00104
12.2880	384	32	170	0.00209
11.2896	256	44.1	100	0.00113
9.126	768	12	106	0.00097
8.1920	256	32	250	0.00205
4.608	384	12	198	0.00091
3.072	256	12	324	0.00100

As can be seen from the table, in general, the higher the frequency, the lower the jitter. But if we describe the jitter in relative parameters, such as unit interval (UI), see the last column of the table, the jitter is comparable. In addition, it can be noticed that the output frequencies 36.864MHz, 33.8688MHz, 24.5760MHz and 12.288MHz can be achieved with different sampling frequencies and scaling factors, which leads to different jitter values. Therefore, when using these frequencies, the user can obtain the lowest jitter by selecting different Fs and scaling factors.